Procedimiento de Validación post-silicio de un microprocesador PWL dedicado (Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture)

Omar David Lifschitz (omar.lifschitz@gmail.com), Juan Agustín Rodríguez (rodrijuana@gmail.com)


Universidad Nacional del Sur.
This paper appears in: Revista IEEE América Latina

Publication Date: July 2011
Volume: 9,   Issue: 4 
ISSN: 1548-0992


Abstract:
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.

Index Terms:
Piecewise linear, Validation, ASIC   


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