Caracterização Arquitetural e Compressão de Código em Processadores Embarcados (Architectural Characterization and Code Compression in Embedded Processors)

Wanderson Roger Azevedo Dias (, Edward David Moreno (, Raimundo da Silva Barreto (

1DCOMP/UFS Departamento de Computação da Universidade Federal de Sergipe
2DCC/UFAM Departamento de Ciência da Computação da Universidade Federal do Amazonas

This paper appears in: Revista IEEE América Latina

Publication Date: June 2012
Volume: 10,   Issue: 4 
ISSN: 1548-0992

This paper presents an architectural analysis of three processors RISC of 32 bits such as: ARM, PowerPC and XScale, used very in embedded systems. Simulation with the SimpleScalar tool was carried through on programs of the MiBench (a benchmark for embedded systems). The experiments show the number of instructions executed, the simulation time (in seconds and processor cycles), issuance of cycles per instruction (CPI) and the percentage of losses in the cache (miss rate) of data and instructions, emphasizing the impact of compression coding of the instructions of the benchmark using the Huffman algorithm, which was around 34% (compression software) for embedded applications, and also compared with an IP core for code compression described in VHDL and prototyped on an FPGA, that showed similar taxes of compression to the Huffman in software, being then of the 32% order (compression in the hardware).

Index Terms:
Architectural Characterization, Compression Instruction, Embedded Processors, Embedded Systems and Simulation Architecture   

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