Técnica Simbólica Basada en Grafos ​​para Mejorar el Análisis de Sensibilidad en Circuitos Integrados Analógicos (Graph-Based Symbolic Technique for Improving Sensitivity Analysis in Analog Integrated Circuits)

Esteban Tlelo Cuautle (etlelo@inaoep.mx), Santiago Rodriguez Chavez ()


INAOE
This paper appears in: Revista IEEE América Latina

Publication Date: Aug. 2014
Volume: 12,   Issue: 5 
ISSN: 1548-0992


Abstract:
Sensitivity analysis methods have been widely applied to electronic circuit design. However, the majority of them are based on formulations dealing with large matrices. That way, this article introduces the application of a new graph-based symbolic technique (GBST) for improving the symbolic sensitivity analysis of integrated circuits (ICs). In addition, the computed sensitivities are ranked to enhance the design and optimization of analog ICs. The proposed GBST is compared with two traditional approaches, namely: adjoint network and incremental network. We show that the three symbolic sensitivity techniques compute the same sensitivity ranking order, while the proposed one is more suitable for amplifiers with a large number of circuit parameters. Two CMOS amplifiers are used as cases of study to highlight the usefulness of our proposed GBST-based approach for performing sensitivity analysis oriented to optimize analog ICs.

Index Terms:
Symbolic Analysis, Sensitivity, MOSFET, Adjoint and Incremental Network, Graph-Based Symbolic Technique   


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