Definição de uma Arquitetura para Configuração de Topologias de Redes Neurais Artificiais utilizando Reconfiguração Parcial em FPGA (Definition of an Architecture to Configure Artificial Neural Networks Topologies Using Partial Reconfiguraton in FPGA)

Carlos Alberto de Albuquerque Silva (carlos77.albuquerque@gmail.com)1, Adrião Duarte Dória Neto (adriao@dca.ufrn.br)1, José Alberto Nicolau Oliveira (nicolau@ufrnet.br)1, Jorge Dantas Melo (jdmelo@dca.ufrn.br)1, David Simonetti Barbalho (davidsb@ufrnet.br)1, Álvaro Medeiros Avelino (alvaro.avelino@gmail.com)2


1Universidade Federal do Rio Grande do Norte (UFRN)
2Instituto Federal de Educação, Ciência e Tecnologia do Rio grande do Norte (IFRN)

This paper appears in: Revista IEEE América Latina

Publication Date: July 2015
Volume: 13,   Issue: 7 
ISSN: 1548-0992


Abstract:
Artificial Neural Networks (ANNs) competence in generalization and reconfigurable hardware using provide a solid base to developing critical embedded systems, capable of efficiently adapt itself as requirements change. Different level adaptation, from physical level up to system level, can be combined to provide efficient solutions using FPGA. So, this work aims to define a novel architecture to configure ANNs topologies using partial FPGA reconfiguration. NEURON block has been described using fixed-point notation and applying partial reconfiguration to load partial bitstreams of sigmoid and hiperbolic tangent functions, as well as dynamically inserting and removing NEURON blocks on the net, this way it is possible to configure MultiLayer Perceptron (MLP) networks with different topologies, using partial bitstreams in reconfigurable areas. It is conceived that, using this kind of hardware facilitates embedding applications using different topologies, MLP ANNs, easily reconfigurable on the field.

Index Terms:
Neural Nertworks Artificial, FPGA, Partial Reconfiguration   


Documents that cite this document
This function is not implemented yet.


[PDF Full-Text (638)]