Propuesta para mejorar el balance entre el número de circuitos satisfactorios y el consumo de potencia en LNA CMOS (A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs)

Jorge Luis González (, Juan Carlos Cruz (, Robson Luiz Moreno (, Diego Vázquez (

1Instituto Superior Politécnico José Antonio Echeverría
2Universidade Federal de Itajubá
3Instituto de Microelectrónica de Sevilla

This paper appears in: Revista IEEE América Latina

Publication Date: Jan. 2016
Volume: 14,   Issue: 1 
ISSN: 1548-0992

This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs.

Index Terms:
CMOS, low-noise amplifier (LNA), variability, yield, radio-frequency receiver, programmable structure   

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