Mecanismos para Provimento de Tolerância a Faltas em uma Rede-em-Chip
(Mechanisms to Provide Fault Tolerance to a Network-on-Chip)
Thiago Felski Pereira (firstname.lastname@example.org)3, Douglas Rossi de Melo (email@example.com)1, Eduardo Augusto Bezerra (firstname.lastname@example.org)2, Cesar Albenes Zeferino (email@example.com)3
1Universidade do Vale do Itajaí (Univali), Universidade Federal de Santa Catarina (UFSC)2Universidade Federal de Santa Catarina (UFSC)3Universidade do Vale do Itajaí (Univali)
This paper appears in: Revista IEEE América Latina
Publication Date: June 2017
Volume: 15, Issue: 6
The constant reduction in the components size of integrated circuits, as well as higher operating frequencies, increases the vulnerability to internal and external noise sources. These noises can cause a failure in any component, affecting the functioning of the system as a whole. Systems-on-Chip (SoCs) with dozens of cores are based on Networks-on-Chip (NoCs), and require networks that are able to detect and prevent a fault in leading to a system failure and an application malfunction. In this context, this work aims at evaluating solutions to increase the reliability and availability of a NoC, implementing mechanisms for error detection and correction. Spatial and information redundancy techniques were applied in order to protect the network against Single Event Upset (SEU) faults. The applied techniques ensured the correct operation of the network in the presence of faults, with low impact to the performance and with acceptable silicon costs.
Systems-on-Chip, Networks-on-Chip, Fault Tolerance
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