Geração de Código Paralelo para a Exploração do Paralelismo em uma Arquitetura Não Convencional (Generating Optimized Code for Parallelism Exploitation to an Unconventional Architecture)

Juliene Vieira do Couto (, Silvio Roberto Fernandes de Araújo (

1Universidade Federal Rural do Semi-Árido

This paper appears in: Revista IEEE América Latina

Publication Date: Oct. 2017
Volume: 15,   Issue: 10 
ISSN: 1548-0992

Along the years, the complexity of processors has increased and with it the demand grows for generating optimized code for them. Therefore, changes in the program, keeping the semantics of the original code and presenting a better performance, known as optimizations are required. The use of non-conventional architectures may be an option for increased performance, as the IPNoSys processor. This processor presents a computer model driven packages which is reflected in its programming model. The objective of this paper is develop the code optimization step in IPNoSys compiler, considering features not explored it, as the parallelism, and even improving your generated code. The optimization modulo offers three levels of optimization. In order to obtain the results a comparison of execution time and memory required of codes generated in the three levels of optimization was performed. The great level optimization reduced at least triple the execution time comparing to no optimized code. Also it was possible reduced the size code by the half in other optimization level.

Index Terms:
Generating Optimized Code, Optimization, Compiler, IPNoSys, Levels of Optimization   

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