5th VLSI Packaging Workshop of Japan

Kyoto, December 4-6, 2000

The Fifth VLSI Workshop in Japan was successfully held in Kyoto. Approximately 50 attended this interactive meeting including 20 from overseas. It was sponsored by and registered with CPMT. This Japanese workshop has been held biannually since it started in 1992. Professor Kanji Otsuka (a current member of the CPMT BOG) was its first Chairman. The present conference Chairman was Dr. Atsushi Nakamura of Hitachi. The General Chair for the 2002 workshop will be Atsushi Nakamura from Hitachi and the Vice Chair will be Max Kohno from Dow Chemical Japan. The attendance was lower than in past years presumably because of two other CPMT-sponsored Asian conferences (held within the same one week period) which limited attendance from Singapore and Hong Kong.

There were a total of 32 half-hour papers plus an afternoon panel session on electrical performance, which was extremely successful. All papers were given in plenary sessions. The papers covered the entire range of packaging as opposed to most present-day workshops that concentrate on one single subject (e.g. flip chip). When people left the workshop they had been exposed to the entire state of the art of electronic packaging.

There were sessions on 3-D packaging for higher density and speed, papers on high-speed electrical performance, CSPs, fine pitch interconnections, thermal characterization and materials, including buildup layers. There were papers on copper conductor chips, wafer level packaging, optical and CCD packaging, and all in all, every imaginable type of packages.

Copies of the 114 page proceedings may be purchased through Dr. Atsushi Nakamura
<nakamura-atsushi4@sic.hitachi.co.jp>

-- submitted by George Harman and Phil Garrou

The Firth VLSI Packaging Workshop of Japan was held in Kyoto Japan from December 4-6, 2000. The IEEE CPMT Society and NIST jointly sponsored this workshop. The goal of this workshop is to accelerate interactions among experts and leaders in various packaging areas of packaging materials, components, assembling processes, manufacturing equipment and package design. The workshop had three invited talks, 28 presentations in 8 plenary sessions, and the panel discussion concerning
"Technologies for high-performance systmes". Sixty engineers and researchers joined in this workshop and had fruitful discussions during 3 days. Approximately 43 attendees were from Japan, ten from the USA, six from east Asia, and one from Europe.

Rambus Inc. suggested good packaging design considerations of high-speed memory bus. NTT showed interesting multi-gigabit CMOS LSI, and Fujitsu proposed low-K material for high-performance, SOI-CMOS LSI in the invited talk.

On Monday December 4th, 5 papers were respectively presented from University of Arkansas, ASET, Tru-Si Technology, ChipPAC, and Tessera concerning "3-D packages" and 4 papers from Fukjitsu, Meisei University, and ASET on "Electrical Performance". The Process/Materials session had three papers from Questech Solutions, Dow Chemical Japan, and Japan REC. The CSP/New Package Structure session had four papers from ASET, University of Tokyo, ChipPAAC, and IZM, and three papers from TechSearch, University of Tokyo, and ASE for the Fine-Pitch Interconnection (1) session. There were four papers from Qualcomm, ASE, Hitachi in the Thermal/Mechanical Characterization session on Tuesday December 5th.

The panel session had a great discussion among six leaders from the USA and Japan with attendees on Tuesday. On the final day, three papers from Toshiba, Oki, and NTT were presented during the Modules and Systems Applications session. The Fine-pitch Interconnection (2) session heard good papers from NIST, Mitsubishi, and University of Tokyo on Wednesday.

The next workshop will be near Kyoto, Japan in November 2002 and the first call-for-papers will be announced soon. Mr. Atsushi Nakamura of Hitachi has been selected as Chair of the next workshop.

-- F. Ishitsuka, Chair of the 5th VLSI Packaging Workshop of Japan

1. Delegation from the CPMT Society Board of Governor's (Leonard Schaper and Phil Garrou) present gift to Fuminori Ishitsuka of NTT who was the General Chair of this Workshop.

2. Picture of all the attendee to the VLSI Packaging Workshop including 20 from around the world.

3. The Board of Governors of CPMT were well represented at this Workshop. One step in keeping communication with members in every region of the world: Koji Nihei, Leonard Schaper, Phil Garrou, E. Jan Vardaman, George Harman, and Kanji Otsuka .