The 6th IEEE CPMT VLSI Packaging Workshop of Japan
The 6th VLSI Packaging Workshop of Japan was held November 12-14, 2002 in Kyoto at the spectacular Kyoto Research Park facilities.
This was a notable occasion because the first one was held
in 1992, making it the 10th year of the workshop in Japan. The
WEB site is still up. Try it and plan for the 7th in 2004.
( http://homepage1.nifty.com/ieeetokyo/chapter/cpmt/vlsip.html
)**
Both the Japanese as well as other attendees made many comments about the very active questioning and discussions. The technical attendance turned out to be 107 with 12 table-top vendor booths (and about 12-15 vendors). Compare this with the 2000, 5th WS, which had only 65 attendees and no vendors. (All hoped that this improved attendance portended an improvement in the electronic packaging economy). Thus everyone is enthusiastic and looks forward to the 2004, 7th, Workshop, again to be in Kyoto.
There were a total of 40 half-hour papers plus invited ones. These were given in three entire days and also one evening session-They worked the attendees hard, but the information gained was worth it!!
The papers covered the entire range of packaging, Including such topics as putting micro-vias through already device-fabbed, thinned, stacked-wafers to shorten the delay times for very high speed processors/cash memory. This is a new hot topic in packaging interconnections! It is the true interface between packaging and wafer fabbing. Other techniques for stacking chips were also discussed (usually called 3-D packaging). Papers on wire bonding, and packaging problems of Copper-Low K chips (TSMC-Taiwan) were given. Also there was an interesting paper on organic semiconductors-they continue to improve. Thermal design, an important subset of packaging, had only one paper devoted exclusively to it, however it was an intergrel part of other packaging issues such as in stacked die, and high performance packaging.
Several papers were given on high-speed electrical performance, fine pitch interconnections, flip chips, soldering, and materials, including buildup layers. Optical and CCD packaging was featured also. It is beginning to look like optical intraconnected MCMs are improving and moving nearer reality!
The 182 Page proceedings, consisting of ~4 page papers was a very professional job and is available from the conference chair until they run out.
In additional to the excellent facilities of the Kyoto Research Park, the food was great, with a special chef preparing tempura that never seemed to run out.
-- submitted by George Harman, NIST .....(also in picture is Mr. Kinya Ichikawa)
Picture 3. Mr. Atsushi Nakamura, Dr. Takeshi Takamori, Mr. Masahiko Kohno
Picture 5. Ms. Silke A. Spiesshoefer, Prof. Len Schaper, Mr. Hideki Osaka, Mr. Risto Tuominen.