Reliability/CPMT/ED Singapore Chapter
SHORT COURSES: 10 December 2002, Tuesday
|0830 - 0900 hrs
||Registration: Level 3 Foyer
|0900 - 1700 hrs
(inclusive of Lunch and two Coffee Breaks)
|SC1: Integrated Passives Technologies: Design, Materials & Processing
Room: Galleria II
|SC2: Active Optical Components for Telecom & Data Applications
Room: Galleria III
|SC3: Wafer Level Chip Scale Packaging Technologies: Application of Solders & Solder Alternatives
|SC4: Lead Free Solder Materials & Reliability Performance
||Dr Swapan Bhattacharya, Georgia Institute of Technology, USA
||Dr Torsten Wipiejewski, Agility Communications, USA
||Dr John Lau, Agilent Technologies, USA
||Dr John Pang, Nanyang Technological University, Singapore and Dr Andreas Schubert, Fraunhofer Institute, Germany
CONFERENCE DAY 1: 11 December 2002, Wednesday
|0730 - 0830 hrs
||Registration: Level 4 Foyer
||Room: Grand Ballroom 1, Level 4
|0830 - 0845 hrs
||Conference Opening Address by EPTC 2002 General Chairman
Charles Lee, Infineon Technologies Asia Pacific
|0845 - 0930 hrs
||Keynote Address: High Densitry Packaging in 2010 and Beyond
by Rao R. Tummala, Georgia Institute of Technology, USA
|0930 - 1015 hrs
Ambient Intelligence - Key Technologies in the Communication Age
by Werner Weber, Infineon Technologies, Germany
|1015 - 1045 hrs
Room: Galleria II & III, Level 3
Room: Cardinal, Level 3
Room: Swallow, Level 3
|1045 - 1225 hrs
||Session A1- MP2:
Lead Free Solders
|Session A2 - AP4:
RF / HF Challenges
|Session A3 - QR1:
Reliability / Failure Analysis I
|1225 - 1335 hrs
||Lunch: Grand Ballroom 1, Level 4
|1335 - 1515 hrs
||Session B1 - MP1:
|Session B2 - AP1:
|Session B3 - QR2:
Reliability / Failure Analysis II
|1515 - 1600 hrs
|1600 - 1740 hrs
||Session C1 - MP3:
Solders and Adhesives
|Session C2 - AP3:
|Session C3 - TE2:
Electrical Design and Test
|1830 - 2100 hrs
||Conference Banquet cum Talk
Room: Lyrebird, Level 3
TABLETOP EXHIBITION: 11 December 2002, Wednesday
|1000 - 1830 hrs
||Level 3 Foyer
CONFERENCE DAY 2: 12 December 2002, Thursday
Room: Galleria II & III, Level 3
Room: Cardinal, Level 3
Room: Swallow, Level 3
|0845 - 1050 hrs
|Session D2 - AP2:
Modules and Integration
|Session D3 - TE1:
Electrical Performance / Signal Integrity
|1050 - 1200 hrs
||Coffee Break / P1: Poster Session / Networking Session
Level 3 Foyer
|1200 - 1325 hrs
Educational Modules Over the Internet: A Demonstration
Paul Wesling, CPMT/Hewlett Packard Co., USA
Room: Grand Ballroom 1, Level 4
|1325 - 1530 hrs
||Session E1 - IA1:
|Session E2 - TE3:
Package Thermal Modeling
|Session E3 - MS2:
Modeling and Simulation II
|1530 - 1600 hrs
|1600 - 1740 hrs
||Session F1 - IA2:
|Session F2 - TE4:
|Session F3 - MS1:
Modeling and Simulation I
|1740 - 1800 hrs
||Presentation of Outstanding Papers and Closing
Level 3 Foyer
Note: The above advance program is subject to changes. Please check the website regularly for updates.
Click here for full version of Final Programme (EPTC2002_FinalProgA4.pdf 278 Kb) with details of papers in each session.
EPTC 2002 SHORT COURSES - 10 December 2002, Tuesday
SHORT COURSE 1: Integrated Passives Technologies: Design, Materials & Processing
Dr Swapan Bhattacharya, Georgia Institute of Technology, USA
The electronics industry is responding to consumer demands for product miniaturization
that requires components to be smaller and packaging to be space efficient. Examples
of such applications include cheaper, smaller, lighter, and high performance computers,
mobile phones, and other electronic products. Embedded passives have received
tremendous attention as a novel emerging technology appropriate for next generation
packaging needs. This course will introduce the merits of embedded passive components
as an alternative to discrete passives and devices currently being utilized. The
various approaches to embedding passive elements in the substrate/package will
be reviewed and the potential impact of embedded passives on future electronic
products will be presented. The course will also discuss modeling, design and
test methodologies for embedded passives. The potential barriers for the economic
viability of embedded passives will be analyzed.
What you will learn:
- Role of passive components in next generation electronics packaging
- Worldwide approaches to passives integration
- Materials and processes for embedded passives
- Critical issues in commercialization of embedded passives
- Embedded/integral passives - Descriptions and definitions
- Why Integral/Embedded passives?
- Electronic system packaging needs (SIA, NEMI, ITRI, Industry perspectives)
- Benefits of integration of passive components
- Design and Modeling of passives
- Materials approaches for realization of embedded capacitors, resistors, and
inductors in MCM-C, MCM-D, MCM-L, and MCM-L/D technologies
- Integral passives research and development activities around the world
- Integral passives and MEMS research at the Packaging Research Center, Georgia
- University and industry prototypes
- Commercialization paths and issues
- Economic and technical viability - integral vs. discretes
- Challenges: Design, modeling, fabrication, characterization, and testing
- The future of embedded passives
Who should attend:
This course is suitable for all levels of engineers and managers involved in R&D,
design, manufacturing, process and product development for electronic systems
and products in automotive, telecommunications, computers, medical, and aerospace
product sectors. This course will be beneficial to packaging engineers involved
in advanced substrate/PWB development for MCM and next generation System-on-Package
Dr. Swapan Bhattacharya received his M.S. and Ph.D. Degrees from the Indian Institute
of Technology, Kharagpur, India. Following his graduate work in Polymer Science
and Engineering, he held several postdoctoral positions with the US universities
in the areas of polymers, ceramics, and high-performance fibers and their composites.
During the period 1987-1995, Dr. Bhattacharya has worked for Systran Corporation,
American Cyanamid Company, and Amoco Corporation. He joined Georgia Tech in 1996
as a Research Faculty. Since then, he has been pursuing research in integrated
passives and low-cost electronics packaging. He has published over 100 technical
papers and edited a book on polymer composites.
SHORT COURSE 2: Active Optical Components for Telecom & Data Applications
Dr Torsten Wipiejewski, Agility Communications, USA
Active optical components are key elements in modern high speed optical transmission systems. The objective of this
course is to give an overview of the various active optical components employed in generic optical transmission
systems. The course will cover the underlying physical principles of these components as well as packaging and
- Introduction: modern optical transmission systems
- Laser diodes: basic design and operation
- Optical gain in semiconductors
- Fabry-Perot laser diodes (structure and fabrication, performance)
- Distributed Feedback (DFB) lasers (properties and applications)
- Vertical-cavity surface-emitting lasers (VCSELs at 850nm, 1300/1550nm)
- Tunable lasers (tuning scheme, applications)
- Laser diode packaging (wavelength monitoring)
- Modulators: different types and speed limitations
- Mach-Zehnder modulator
- Electro-absorption modulator (chirp performance)
- Photodetectors: the receiving side of a transmission system
- Pin photodiodes (responsivity and bandwidth limitation)
- Avalanche photodiodes (gain and noise performance)
- Other photodetectors (MSM, heterodyne detection)
- Integration: technical challenges and economic boundary conditions
- Types of integration and limitations
- Laser diode and electro-absorption modulator
- Outlook on future developments
Who should attend:
Engineers and technical managers who want to gain a fundamental understanding of the characteristics of various
active components used in modern and future optical transmission systems.
Dr. Torsten Wipiejewski is currently Director of Advanced Technology and Program Manager at Agility Communications. He
received a M.Sc. degree in Electrical Engineering from the Technical University of Braunschweig, Germany, in 1990 and
a summa cum laude Ph.D. degree from the University of Ulm, Germany, in 1994. The Ulm University Society awarded his
Ph.D. thesis on VCSELs with the "Best Ph.D.-Thesis Award". He continued to work on novel VCSEL devices during a
two-year post-doctoral stay at the University of California at Santa Barbara, CA. In 1996 Torsten Wipiejewski joined
Siemens Fiber Optics, where he worked as VCSEL project manager at different locations in Germany. The VCSEL project
was awarded with the "Innovations Award" of the Siemens Semiconductor Group (now Infineon Technologies) in 1999.
Before joining Agility, Torsten Wipiejewski was the general manager of the Optoelectronic Components Group of Infineon
Fiber Optics in Munich, Germany. He has authored or co-authored more than 70 publications and over 20 patents and was
awarded Infineon's "Inventor of the Year" in 1999. Torsten Wipiejewski is a member of the IEEE LEOS and CPMT and a
member of the ECTC Optoelectronics program committee.
SHORT COURSE 3: Wafer Level Chip Scale Packaging Technologies: Application of Solders & Solder Alternatives
Dr John Lau, Agilent Technologies Inc, USA
What You Will Learn:
This course gives you fundamental principles, engineering data, and cutting edge information on the most important
development and latest research results in applying the lead-free soldering and conductive-adhesive technologies to
low-cost, high-density, and reliable wafer level chip scale packages (WLCSP). For professionals active in WLCSP,
lead-free and conductive-adhesive research and development, those who wish to master the lead-free and
conductive-adhesive problem solving methods, and those demand a cost effective design and high-yield environmental
benign manufacturing process for their low-cost and high-density WLCSPs, this course is a timely summary of progress
in all aspects of this fascinating field.
After this course, you will develop a practical understanding of the cost, design, materials, process, equipment,
manufacturing, and reliability issues of WLCSP, lead-free, and conductive-adhesive technologies. The material is based
on the newly published handbook, Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive
Materials (McGraw-Hill) authored by John Lau, C P Wong, Ning Cheng Lee, and Ricky Lee.
Who Should Attend:
This course meets the needs of design, materials, process, equipment, manufacturing, quality control, product
assurance, reliability, component, packaging, marketing, and system engineers, and technical managers
working in electronic, photonic, and MEMS packaging and interconnection.
- Critical Issues of WLCSPs
- Lead-free soldering activities in Europe, Asia, and USA.
- Criteria, development approaches, and varieties of alloys and properties of lead-free solders.
- Physical, mechanical, chemical, electrical, and soldering properties of lead-free solders.
- Chip (wafer) level interconnects with lead-free solder bumps - various UBMs.
- Lead-free solder wafer-bumping with micro-ball mounting and paste printing methods.
- Microvia Technologies.
- PCB/substrate with build-up layers connecting through Microvias.
- Lead-free solder-joint reliability of WLCSPs on organic and ceramic substrates.
- Chip (wafer) level interconnects with solderless bumps such as Ni-Au, Au, and Cu; solderless wires such as Cu and
Au; and solderless studs such as Au and Cu.
- Adhesives:- isotropic conductive adhesives, anisotropic conductive adhesives, non-conductive adhesives, and
- Design, materials, process, and reliability of various solderless WLCSPs with various adhesives on
John H. Lau is an interconnection technology scientist at Agilent Technologies, Inc. He received his Ph.D. degree in
Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering
from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of
Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also
has a B.E. degree in Civil Engineering from National Taiwan University (1970). His current interests cover a broad
range of optoelectronic packaging and manufacturing technology.
Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory,
Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years experience in various
fields, he has given over 200 workshops and invited presentations, authored and co-authored over 200 peer reviewed
technical publications, authored more than 100 book chapters, and is the author and editor of over 14 popular books
in IC packaging. John served on the editorial boards of the IEEE Transactions on Components, Packaging, &
Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging, and has chaired several conferences,
conference programs and technical sessions. He is a Fellow of ASME and IEEE and is listed in American Men and Women of
Science and Who's Who in America.
SHORT COURSE 4: Lead Free Solder Materials & Reliability Performance
Dr John Pang, Nanyang Technological University, Singapore and Dr Andreas Schubert, Fraunhofer Institute, Germany
Lead-free solder materials are emerging to replace tin-lead solders in electronic assemblies as the industry adapts
to legislations and environmental lobby to ban lead in electronic products. Implementation of lead-free solders in
electronic packaging involves knowledge of lead-free solder materials characterization and mechanical properties,
solder joint reliability tests and failure analysis, finite element analysis simulation and fatigue life prediction.
Who Should Attend:
Design, manufacturing, quality and reliability professionals who are responsible for implementing lead-free electronic
packaging and surface mount technology (SMT) electronic assemblies.
What You Will Learn:
This Workshop will provide updated knowledge on lead-free solder materials and reliability performance. A Design For
Reliability (DFR) methodology employing solder materials testing, modeling, non-linear finite element analysis and
fatigue life prediction will be presented along side experimental reliability test results. Finite element analysis
(FEA) modeling of board level solder joint reliability assessments for lead-free and tin-lead materials will be
presented. Solder joint reliability test results will be covered.
- Lead-Free Bulk Solder Mechanical Properties
Lead Free Solder Joint Reliability Tests and Analysis
- Mechanical properties of lead-free (SnAg, SnCu, SnAgCu) versus SnPb solders, Effect of Temperature and Strain Rate
- Fatigue properties of lead-free (SnAg, SnCu, SnAgCu) versus SnPb solders, Effect of Temperature and Frequency
- Creep properties of lead-free (SnAg, SnCu, SnAgCu) versus SnPb solders, Effect of Stress and Temperature
Finite Element Analysis and Modeling
- Creep and Stress Relaxation, Bulk versus Joint behavior (SnAg, SnAgCu, and SnPb)
- Temperature cycle data on FCOB with/without underfills, CSPs and BGAs at different test conditions
and solder alloys types
- Solder-surface finish interactions, intermetallic growth, metallization consumption, intermetallics
within the solder, thermo-mechanical properties of the intermetallics.
- Failure mechanisms related to the solder joints of the new alloys, will creep deformation still play
a dominant role for e.g. thermally induced low cycle fatigue?
- Material constitutive models - implementation of time and temperature dependent behavior of solders
(SnAg, SnAgCu, and SnPb).
- Life prediction models - Strain-based relations (accumulated creep strain), Energy-based relations
(average viscoplastic strain energy dissipated).
- FEA modeling and simulation of Thermal Cycling Tests (SnAg, SnAgCu and SnPb), Comparison between
simulation results and experimental results.
John H.L. Pang is an Associate Professor in the School of Mechanical and Production Engineering at Nanyang
Technological University, Singapore. He is Director of the Electronic Packaging Strategic Research Programme. He
received his PhD in 1989 and BEng in 1985 from the University of Strathclyde, Scotland. His research interests are
in the areas of design-for-reliability in electronic packaging, non-linear finite element analysis, solder joint
reliability, fatigue and fracture mechanics of materials failure.
Andreas Schubert is the Head of the Fracture Electronics Group, Fraunhofer IZM, Berlin, Germany since 1993 and Vice
Head of the Department of Mechanical Reliability and Micro Materials, Fraunhofer IZM, Berlin, Germany since 1998. He
received his PhD (Material Science) in 1985 from the Mining Academy in Freiberg, Germany. Dr. Schubert's areas of
expertise include mechanical and thermal reliability aspects; advanced packaging technologies; numerical
(FE simulation) and experimental (X-ray, materials testing, scanning electron microscopy) investigations.
Last edited: Oct 17, 2002.