ASTR
2005
ASTR
2005
Workshop on Accelerated
Stress Testing & Reliability
Sponsored by the IEEE/CPMT ASTR Committee and Technically co-sponsored by the IEEE Reliability Society
ABSTRACTS
Accelerated Life Testing (Alt) In Micro- And Opto-Electronics: Its Role, Attributes, Challenges, Pitfalls, And Interaction With Product Development And Qualification Tests
By:
E. Suhir,
Dr. Ephraim Suhir
University of California
Abstract:
Course objectives: Describe different categories of accelerated tests, discuss their role and attributes in micro- and especially in opto-electroinic and photonic engineering, challenges and pitfalls associated with the implementation and use of ALTs, as well the interaction of the ALTs with qualification and product development accelerated tests. Address the differences in the ALTs for micro- and opto-electronic systems.
Course description: We discuss the role, attributes, challenges, and pitfalls of the ALT in micro- and opto-electronic packaging, as well as its interaction with product development and qualification testing. The emphasis is on the opto-electronic and photonic engineering. Since ALTs cannot do without constitutive equations, we address also the role of predictive modeling, both analytical (“mathematical”) and computer-aided (“simulation”). The area of thermal stress failures in micro- and opto-electronic systems is used to illustrate the discussed concepts. Particularly, we examine thermal stress failures in bonded and solder joints; in thin film structures; in polymer-coated optical silica fibers and in fibers adhesively bonded into capillaries or soldered into ferrules. We indicate also the role that a probabilistic approach should play in understanding of the effect of the variability in materials properties, structural geometry and loading conditions.
Reliability Integration Across the Product Life Cycle
By:
Mike Silverman, CRE
Managing Partner
Ops A La Carte, LLC
Abstract:
Good engineers naturally consider reliability aspects of product design and manufacturing. Management teams typically fully specify cost, performance and time-to-market criteria, building a fairly complete product development and manufacturing plan. However, the reliability aspects of this plan are usually very short, incomplete and not tailored to the specific product. Having well-defined goals with appropriate metrics is an important first step to achieve overall product and reliability objectives.
Once our goals are defined, we must then choose a set of reliability tools and techniques to achieve our goals. Choosing the appropriate reliability tools and techniques involves understanding the basic market and technology driven reliability constraints, along with an appreciation of the benefits of a wide range of reliability tools and techniques.
Because each product and company is different, reliability programs must be tailored to each situation. Generally speaking, there are two approaches to achieving product reliability objectives: 1) Accelerated Techniques such as HALT & HASS; and 2) Classical Techniques such as Predictions and Verifications. A good reliability program requires a balance between the two approaches and a subset of reliability tools and techniques from each.
Next we must seamlessly and cohesively integrate all of the reliability tools and techniques together that we have chosen to maximize reliability at the lowest possible cost.
This presentation provides an outline of how to quickly assess your product’s situation, define your reliability goals, narrow down the appropriate reliability tools and techniques, and then integrate these together in your reliability program.
Power Conversion Reliability
By:
Don Gerstle
C&D Technologies
Abstract:
Power conversion reliability is crucial to overall system reliability. There are key steps to ensure success here. An introduction to this is made by defining reliability and different ways of calculating MTBF.
A list and explanation of some of the key steps for controlling the design and manufacturing process follows. This includes comprehensive specification development, good design processes, and proper component selection. Thermal aging in magnetics, cracked SMT capacitors, opto-isolator CTR degradation, and connector fretting are some of the problem areas covered, with methodology outlined on dealing with each of these issues.
The impact of testing processes on reliability is covered, with sample size versus expected production yield statistics. Tin whiskers can affect reliability. This tells where they occur, what problems they cause, and how to best deal with them. Future reliability trends are the final subject matter, with a number of areas presented, including prognostics for early problem detection and improved burn-in. Numerous pictures, graphs, and charts are used to support and clarify points made during the presentation.
Novel and Robust Electrostatic Discharge (ESD) Solution in CMOS Technology
By:
Juin J. Liou
University of Central Florida
Abstract:
Electrostatic discharge (ESD) is a process in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and more than 35% of chip damages can be attributed to such an event. An overview on the ESD sources, models, and protection solutions will first be given in this talk. Then the development of a robust ESD solution for protecting data communication transceivers will be presented.
Environment and Usage Monitoring of Electronic Products for Health (Reliability) Assessment and Product Design
By:
Nikhil Vichare, Peter Rodgers, Valerie Eveloy, and Michael G. Pecht
CALCE Electronic Products and Systems Center, University of Maryland
Email: pecht@calce.umd.edu
Abstract:
A significant proportion of the US industry is devoted to systems intended for operation over a long life cycle. Examples of such systems include aerospace, automotive, telecom infrastructure, oil exploration and military applications. Their long-term reliability, often 10 – 20 years, is essential and maintenance opportunities are frequently limited by accessibility, as well as logistical, operational and economic constraints.
Prognostic health monitoring (PHM) permits the reliability of a system to be assessed in its actual application conditions. Thus by determining the advent of failure, based on actual life cycle application conditions, procedures can be developed to mitigate, manage and maintain the system. One method of implementing PHM is by monitoring the environmental and usage loads experienced by the product in its life cycle and utilizing them for real time or near real time health assessment. In this approach, one of the challenges faced is to effectively collect the life cycle data for in-situ health assessment.
In this paper, an integrated hardware-software micro-programmable module for health and usage monitoring of electronic products in their application environment is presented. The hardware incorporates local sensors, and on-board processing power using embedded software. These data processing capabilities would enable immediate and localized processing of the raw sensor data and provide operational efficiencies in terms of power and memory consumption in the application. Guidelines are provided to develop a life cycle monitoring plan, that encompasses the selection of environmental and usage parameters. A case study is presented to illustrate the methodology.
Heat Sink Fouling in Air-Cooled Electronics
By:
Aharon Nabi, Peter Rodgers, and Avram Bar-Cohen
CALCE Electronic Products and Systems Center, University of Maryland
Abstract:
With the reduction of heat sink thermal design margins, which has resulted from rising processor heat dissipation, system miniaturization and fan acoustic noise constraints, the impact of fouling on heat sink thermal resistance (thermal and hydraulic performance) has become much more critical than in the past. This impact is most pronounced for fine-pitch heat sinks, which are commonly employed for computer cooling. The resulting loss of heat sink cooling effectiveness makes air-cooled desktop computers prone to self-protection shutdown, even in standard office environments. To maintain product performance and reliability, methods of minimizing heat sink fouling, such as anti-dust accumulating heat sink design features and filter design, require to be investigated. This requires an understanding of the mechanisms of heat sink fouling and its impact on thermal performance, as a function of contaminant and application environment.
In this paper the process of heat sink fouling is analyzed in terms of deposition, adhesion and thermal performance degradation. Dust collected from electronic equipment operated in office environments was chemically analyzed to determine the typical airborne contaminant characteristics. Based on the findings, both anti-dust accumulating heat sink features, and possible methods for freeing dust accumulation are discussed.
Test Methodology to Determine Durability of Interconnects under Board Level Drop Testing Conditions.
By:
Joseph Varghese, and Abhijit Dasgupta
CALCE Electronic Products and Systems Center, University of Maryland
Abstract:
This paper is part of an ongoing effort to develop a test methodology to determine the durability of surface mount interconnects under impact loading conditions. Literature indicates that as the drop height is increased, there is a transition in the failure site from the ductile solder to the brittle intermetallic or the copper traces. Not much work has been done to understand this phenomenon. This study considers deformation energy accumulated in the interconnects in terms of the local strain in the printed wiring assembly (PWA), local strain rate and component acceleration. The advantage is that the results are less dependant on structure and loading, because the deformation is quantified in terms of specimen response rather than the loading conditions.
A simple test specimen is fabricated to concentrate the study on interconnect failure mechanisms. An instrumented, repeatable test setup is developed to conduct high speed bend tests and drop tests on the specimen. All tests are replicated twice for proof of consistency of the test data. As expected, the durability of the specimen decreases monotonically with PWA strain. On the other hand, the durability first increases and then decreases as the PWA strain rate increases. Failure analysis shows a transition in the failure site with strain rate. It is hypothesized that for a given package design, the rate dependent material properties determine the partitioning of the strain energy of deformation. Yield stress of the ductile materials and fracture toughness of the brittle materials are identified as the key parameters. Finite element analysis is used to correlate the PWA strain, PWA strain rate and component acceleration to deformation at the failure site. A failure envelope is created to estimate the damage in the interconnect under various loading conditions. The end goal is to develop a consistent, accurate and generic methodology for ranking the impact durability of different surface mount interconnects technologies.
Identification and Utilization of Failure Mechanisms to Enhance FMEA and FMECA
By:
Sathyanarayan Ganesan, Valerie Eveloy, Diganta Das, and Michael G. Pecht
CALCE Electronic Products and Systems Center, University of Maryland
Abstract:
Failure mechanisms are the processes by which physical, electrical, chemical and mechanical stresses induce failure. Knowledge of the failure mechanisms that cause product failure is essential to design and qualify reliable products. The standard Failure Modes and Effects Analysis (FMEA) and Failure Modes, Effects and Criticality Analysis (FMECA) procedures do not identify the product failure mechanisms and models, which limits their applicability to provide a meaningful input to critical procedures such as virtual qualification, root cause analysis, accelerated test programs, and to remaining life assessment. This paper proposes a new methodology, namely Failure Modes, Mechanisms and Effects Analysis (FMMEA), which enhances the value of FMEA and FMECA by identifying high priority failure mechanisms and failure models. High priority failure mechanisms determine the operational stresses, and the environmental and operational parameters that need to be controlled. Models for the failure mechanisms help in the design and development of the product. The proposed FMMEA methodology is applied to an electronic circuit board assembly mounted in an automotive underhood environment.
Utilizing Reliability Testing to Overcome Pb-Free Assembly Challenges
By:
Randy Schueller, Dell Component Engineering Manager - Mechanical Group
Abstract:
As electronic manufacturing switches from Pb Sn solder to Pb-free solder there are several potential defect mechanisms that are unique to the process. This presentation will present and discuss those defect mechanisms and some of the stress testing methods that have been useful in precipitation and detection of these defect types.
Dielectric Integrity Test for Flip-Chip Devices with Cu/Low-k Interconnects
By:
Charles Odegard, Tz-Cheng Chiu, Cheryl Hartfield, Vish Sundararaman
Texas Instruments Incorporated
Dallas, Texas
Abstract:
Migration to low-k dielectric materials for back-end-of-line (BEOL) dielectrics is necessary for improved electrical performance and enabling smaller geometries in circuit design. Unfortunately, these low-k materials have weaker mechanical properties compared to previous generations of dielectric materials. Concurrently, market driven changes in flip-chip packaging such as tighter bump pitch and replacing SnPb with lead-free solder bump composition are leading to increased stress in flip-chip packages. This combination of increased sensitivity to stress and increased magnitude of package stress results in significantly increased risk of dielectric damage in flip-chip packages for current and future silicon technology nodes that requires low-k dielectrics. Given the high-risk to mechanical damage of the low-k dielectrics in a flip-chip package, it is critical to characterize the structural integrity of the BEOL interconnect layers containing low-k dielectrics. Standard reliability testing, however, is both time-consuming and expensive, and therefore not desirable during early development of the new silicon technology node. It is preferable to have a fast, inexpensive dielectric integrity test that will accurately predict mechanical performance of the BEOL structure during the development phase.
This paper presents a novel thermomechanical test for investigating the integrity of Cu/low-k BEOL structure. In this test a silicon die with Cu/low-k interconnect is assembled to an organic substrate through flip-chip bumps. The assembly is then subjected to various degrees of temperature cooling. The thermal residual stress due to the coefficient of thermal expansion (CTE) mismatch between the silicon die and organic substrate would cause failure to occur if the residual stress exceeds the strength of the structure. Finite element simulation for the test structure indicates that a localized stress concentration zone, composed of mixed-mode peel and shear stresses, is present underneath the edge of each solder bump. The stress concentration could lead to cracking if stress level is reaching the cohesive or adhesive strength of the low-k dielectric material. Since the level of thermal residual stress depends on the temperature, the magnitude of stress experienced by the low-k dielectric structure can be easily controlled by subjecting the test sample to various degrees of cooling. Consequently, the level of stressing required to induce fracture and the strength of the specific material/interface of failure can be determined from this test.
Failure detection for the dielectric integrity test is conducted by pulse-echo mode of scanning acoustic microscopy (C-SAM). Areas with BEOL interconnect damage, either due to cohesive fracture of the low-k dielectric or adhesive delamination between the low-k dielectric and adjacent layer will appear brighter than non-damaged areas, due to the increased magnitude of reflected sound-wave at the discontinuity of the damage site. Mechanical and focused ion beam (FIB) cross-sections are then done to confirm and further characterize the cohesive and/or adhesive dielectric damage.
In this study a silicon die with multilayer Cu/low-k interconnect structure was attached to an organic substrate using either SnPb or Pb-free solder bumps. The sample was then subjected to 22C, -25C, and -50C to expose the Cu/low-k layers to various levels of thermomechanical stresses. C-SAM and FIB cross-section analysis was then performed on the samples. Results of the dielectric integrity test showed that failure mode and location has strong correlation to predictions from finite element simulation. First, it was observed that damage of the low-k dielectric occurred more under bumps at the corners and edges of die than bumps closer to the die center. It correlates to the prediction that stress increases with distance from the die center. Second, it was found that samples with Pb-free SnAg solder bumps had more dielectric damage than samples with SnPb solder bump at any given temperature condition. This verified the prediction that the solder material affects the magnitude of stress. Since SnAg solder alloy has higher melting temperature and is stiffer than the eutectic SnPb alloy, the sample with SnAg bump has higher thermal residual stress when it cools down from die attach solder bump reflow, and consequently, results in more damage than the sample with SnPb solder.
Reliability Evaluation of Printer Lead Free PCBAs
By:
Aamir Kazi
Dell Reliability Engineering, Austin, TX 78682
Pratap Singh
RAMP Inc. Round Rock, TX 78681
Abstract:
In order to comply with RoHS requirements for electronics products by July 2006, all printer products at Dell Inc. are converting to use of lead free solder for printed circuit board (PCB) and card assembly. The lead free solders, even though stronger than tin-lead solders, are brittle in nature and produce solder joints with shrinkage cavities or cracks. Such sites may form starting points for solder joint crack development under thermo-mechanical stresses. These solders also require higher processing temperatures during surface mount reflow, wave solder assembly and component rework.
The most common lead free solder used for reflow processes is tin-silver-copper (Sn-Ag-Cu) alloy called SAC and for wave solder it is a tin-copper (Sn-Cu) alloy. The higher processing temperatures (240-260o C for SAC solder vs. 200-220o C for tin lead solder) cause higher stresses on PCBs and components and has raised concerns about solder joint reliability and component damage. This investigation of printed circuit board assemblies that have gone lead free was started to address these concerns.
The test evaluations show that pin solder joint for single sided boards are a reliability risk especially with bulky components. Even double sided and multilayer board pin solder joints become a reliability risk when plated through holes (PTH) have poor solder fill during wave solder process. Pre and post test metallographic micro sections are provided to explain the test observations. Recommendations are made to improve the pin solder joint reliability for all board types as each board transitions to lead free assembly.
Tyco Power Systems Design and Test For Reliability
By:
Paul T. Parker
Tyco
Abstract:
Tyco Electronics Power Systems Utilizes a Reliability strategy heavily focused on up front automated design practices following Design Guidelines based on our understanding of Physics of Failure. Many of our Design Guidelines are based on Component level Accelerated Testing focused on specific failure mechanisms.
By understanding root cause of power supply failures, designs can be optimized to their use environment to provide long term reliability at reasonable costs.
Designs are tested using standard qualification practices as well as tools of HALT and HASS early in development. Rapid Reliability growth can be obtained using HASS and production yield management during manufacturing.
Feedback on lessons learned is collected during Design, Production and Field Use and incorporated in a lessons learned data base to provide constant feedback for long term improvement.
Application of Accelerated Testing Techniques to Enhance Reliability and Durability of the DoD Identification Smartcard
By:
John Fessler
Abstract:
This talk will focus on pre- and post-issuance testing techniques which have been implemented to enhance durability and reliability in the Common Access Card (CAC) within the Department of Defense. The CAC is the new Java-based identification smartcard that provides logical and physical access the Department of Defense computer systems and based and is deployed worldwide to more than 4 million military and civilian personnel.
Software Fault Isolation using HALT and HASS
By:
Ken Franks
Allied Telesyn
Abstract:
The establishment of Allied Telesyn’s Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) processes has followed a traditional path—from the original proposal and initial rejection to the implementation and subsequent acceptance of the principals applied and the value gained from conducting Accelerated Stress Testing.
Throughout this journey, one topic has always appeared under reported. HALT discovers an appreciable amount of faults that are attributed to software.This white paper focuses on the discovery of these failures, the isolation techniques involved, and provides examples of software faults found at Allied Telesyn.
COTS Parts and HALT as Applied to the Tactical Tomahawk Missile
By:
Terry Tracy, Senior Principal Engineer with Honors
Raytheon Missile Systems
Abstract:
In the spirit of acquisition reform, a major upgrade to the Tomahawk missile was proposed by Raytheon Missile Systems as an unsolicited bid to increase performance, reduce cost by half, and significantly improve reliability. As proposed, the design incorporated COTS parts including PEMS resulting in an eventual 95% design penetration. In order to assure improved reliability while using commercial, industrial–grade parts, a modification of the Highly Accelerated Life Testing concept originated by Greg Hobbs was employed to maximize detection of design weaknesses while optimizing confidence in the test results. HALT provides the opportunity for a high rate of reliability growth through:
• Rapid identification of design, process and part weaknesses;
• Immediate or expedited corrective actions; and
• Immediate verification of the effectiveness of proposed corrective actions.
The success of this approach has been demonstrated by the highly successful demonstration test flights of Tactical Tomahawk.
This presentation covers:
• The Raytheon Missile Systems “Layered” HALT approach and how it optimizes knowledge of environmental capability from limited samples;
• The Tactical Tomahawk experience with COTS, PEMs and HALT;
• Lessons learned and changes incorporated into the HALT approach;
• The validation of the HALT approach from demonstration test flights; and
• Development of HASS profiles and Proof of Life techniques.
Utilizing AST as a comprehensive approach for bringing product to market.
By:
Mike Wells
Intertek ETL Entela
Abstract:
When designing and engineering new product, the longer the process takes, the higher the overall cost of the product’s development. This increase in cost will be reflected as diminished return on that particular product. In this presentation, I will describe how we were able to use Accelerated Stress Testing on an automotive interior subassembly to save months in testing time while providing concise information so design iterations could be made and still be able to bring the product to market while meeting strict time requirements along with a high rate of return.
Curvature measurements on PCB : experimental set-up and application for acoustical excitation
By:
François Lafleur, P. Eng., Ph.D.
CRIQ, Montréal, Canada
Abstract:
Board flexing in the product service life, inside the manufacturing process or at the testing stage can cause failure of good electronic component. It is important to be able to detect and measure board flexing to avoid unnecessary components or PCB failure. A theoretical derivation allowed to measured board radius from three displacement measurement. This method is coherent with other published results (Stewart and Linton 2004). This article will present the experimental test setup that was designed to allowed these PBC flex radius measurement. The particular case of PCB testing in the HALT and ESS process was addressed. The manufacturers do not allowed more than a specific radius while the board is insert in the test fixture or when daughter boards or connectors are plug in the UUT (Unit Under Test). So the experimental test setup allowed to measured PBC flexing while inserted in the test fixture and when an external force is applied to the board. The particular case of acoustical excitation with ESSAD will be addressed and example of standard board format (ATX, Micro ATX, ..) fixture qualification will be resented.
A Holistic Approach to Reliability Assessment Using Adaptive Database Management
By:
Craig Hillman, Nathan Blattau and Mikyoung Lee
DfR Solutions
Abstract:
Reliability engineers can often be perceived as roadblocks to product development. The main reason for this perception is the resources necessary and time required to ensure product reliability. The use of computer simulations to reduce resources is a desired goal but still has not been achieved with available software tools. Very often the time required to use these tools is longer than the time required to conduct verification tests. When given the choice, the engineer will always pick testing because it yields data that is widely accepted as verification of a product’s robustness.
One of the main reasons for the lengthy times required for simulations is the fact that reliability engineers are rarely supplied with the necessary information. This is becoming even more of an issue as original design manufacturers (ODM) are becoming increasingly popular. The engineer may be required to assess the reliability of a design with little more a gerber file, a bill of materials (BOM), and a few prototypes.
Aperio PCB uses standard manufacturing data and automatically imports it along with the bill of materials to generate the models necessary to conduct computer aided reliability assessment or “virtual qualification”. The intelligent interpretation of the BOM using an adaptive parts database allows for the generation of part level mechanical, thermal and electrical models. These models and the board structure allow for a range of simulations to be conducted, resulting in a truly holistic approach to product reliability. This paper will discuss the programming architecture, the output, and the validation of Aperio PCB.
Accelerated Serviceability Stress Test (ASST)
By:
Karthik Balasubmaranian
Whirlpool Corp.
Abstract:
The ASST follows the same MEOST principle of stressing the DUT faster, but it is much more cost efficient. On the flip side it is longer and does not cover a huge inference space as the MEOST. The ASST consist of series of teardowns and builds with machine test time attached to it. The test plan for example, may be 10 teardowns and 500 hours of testing. The testing time, teardown level (tear down to how many substrates) and the numbers of teardowns are again based on the knowledge of the products and/or the subcomponents USL and LSL. Any other additional stress available can and should be used along with the service stress. This paper attempt to explain some case studies and pros/cons associated with this form of testing.
Synthesizing a Concise, Exhaustive, Cost effective Accelerated Validation Plan.
By:
Alexander (Alex) J. Porter
Engineering Development Manager
Intertek ETL Entela
Abstract:
Although many accelerated testing techniques are available to speed up the production of data in the testing environment, a complete validation plan can still be slow and cumbersome. This paper will examine a method for synthesizing a complete validation plan using the most efficient set of tests possible to validated the assumptions inherent in the design and the business plan while working within the constraints of the business time line and the available resources.
Random Vibration Kurtosis Control
By:
John Van Baren
President
Vibration Research Corporation
Abstract:
Many test personnel have recognized that random testing, while good, has short-comings when it comes to simulating the real-world environment. As a result, there have been many vibration testing method modifications to address these shortcomings.
One method that has recently become popular is time history replication. Technicians measure the waveform in the field, and produce the same waveform in the lab. This is like “shaped” random in a way, because the spectrum is the same as seen in the real application. This method is good, but also has its shortcomings. It is difficult to find a representative waveform, especially in aerospace applications. When one is obtained, it is representative of a particular situation of the product. Unfortunately, it is probably not representative of the entire life of the product.
Another method used extensively in the automotive world is the HALT and HASS test techniques. Focusing on the vibratory part of these test methods, you see that high level
“random” shock pulses are applied to a product, while pretty much ignoring spectrum content. This has been successful, in part, because of the high level shock pulses applied to the product. These high level pulses are seen in the real-world. Ignoring the spectrum, and concentrating on the shock levels has resulted in some successes.
Other obvious modifications to Random are Sine-on-Random and Random-on-Random. These also attempt to get closer to the real dynamic vibration world. A third modification, called Shock-on-Random is desired by many because they have recognized that random vibration testing alone does not produce the occasional shock pulses seen in the real-world that ought to be found in their random tests. However, what they really are asking for is a way to get higher occasional peaks from standard random tests. This is not Shock-on-Random. This is Kurtosis Control. The rest of this paper describes a newly developed method of random kurtosis control, or sigma stretching, and presents results of a simple, effectiveness-demonstration test conducted in the Vibration Research Corporation laboratory, using this method.
Alternative Metrics for Random Vibration Testing
By:
Gilbert Bastien, MSME, P.E.
Screening Systems, Inc
Abstract:
The business of AST has shown random vibration users over the years that G’s are not a good metric for measuring random vibration. PSD gives a better view of the energy level and characteristic of the vibration spectrum but falls short in providing insight to the actual effect of the vibration input from the vibration table to the Unit Under Test (UUT). The purpose of this presentation is to share an alternative metric for the random vibration spectrum, which actually shows the effect of the input vibration and what it can do (or not do) to the UUT to help reveal defects and weaknesses. This metric is called “J’s.” A specific example will show how this metric is useful in finding defects that no other metric could.
New Technology in Vibration for AST
By:
Gregg K. Hobbs, Ph.D., P.E.
Abstract:
1) The problem: All axis pneumatic vibration systems in the past have not been able to even simulate the real world in terms of low frequency vibration, much less stimulate to accelerated levels. The hydraulic systems are limited to low frequencies.
2) Discuss the real world levels of vibration in terms of spectra versus frequency.
3) Levels and spectra that are required to get sufficient acceleration of failure modes.
4) The new technology
All axis pneumatic systems, some improvements have been made. Spectra and balance.
Combined hydraulic and pneumatic. Spectra and balance obtainable.
Combined electronic and pneumatic. Spectra and balance obtainable.
5) Spectra shaping devices that are now available.
6) Why calculation of the GRMS should be over certain bandwidths depending on the environment and the product under test..
7) Applications for the new technology: AST!
8) Conclusions
The Fiber Menace – Dust testing in the 21st century.
By:
Dave Rahe
PTI Test
Abstract:
The trend for faster processors in smaller system packages has lead to many innovative heat-sink designs. These designs commonly use fine pitched fins with forced air to provide efficient heat removal. With the use of these tightly spaced fins, a new problem has arisen. Fibrous dust particles can quickly accumulate in these heat-sinks reducing airflow and rendering them ineffective. The excessive temperature rise causes reduced system performance, intermittent system operability, and generally intermittent thermal shutdown. Higher part temperatures can also lead to shorter component life an overall reduced reliability.
Established test methods and test equipment only address particulate dust testing. These methods cannot duplicate the fibrous dust failure mechanisms. This paper addresses newly established practices and equipment developed specifically for accelerated fibrous dust testing.