ASTR 2005

Workshop on Accelerated Stress Testing & Reliability

Sponsored by the IEEE/CPMT ASTR Committee and Technically co-sponsored by the IEEE Reliability Society

SCHEDULE

Schedule subject to change.  Last revised 9/15/2005

  Day 1,  Mon  Oct 3   Day 2,  Tue  Oct 4   Day 3,  Wed  Oct 5
7:00 AM   Breakfast   Breakfast   Breakfast
7:05 AM      
7:10 AM      
7:15 AM      
7:20 AM      
7:25 AM      
7:30 AM            
7:35 AM      
7:40 AM      
7:45 AM      
7:50 AM   Introduction Key Note Paul Parker - key note / intro    
7:55 AM    
8:00 AM Reliability Tools A Holistic Approach to Reliability Assessment Using Adaptive Database Management 

Craig Hillman, Nathan Blattau and Mikyoung Lee

DfR Solutions
8:05 AM Key Note Mr. Stuart D. Caffey, Vice President, Desktop/Portables Development

Dell, Inc.

 Tutorial  
8:10 AM  
8:15 AM  
8:20 AM Physics of Failure Identification and Utilization of Failure Mechanisms to Enhance FMEA and FMECA

Sathyanarayan Ganesan, Valerie Eveloy, Diganta Das, and Michael G. Pecht

CALCE Electronic Products and Systems Center, University of Maryland

  
8:25 AM Power Conversion Reliability
8:30 AM  
8:35 AM Don Gerstle
8:40 AM   Highways Of Technology Road Map And Reliability

William Chen 
8:45 AM C&D  Technologies
8:50 AM  
8:55 AM  
9:00 AM Novel and Robust Electrostatic Discharge (ESD) Solution in CMOS Technology

Juin J. Liou

University of Central Florida

  
9:05 AM  
9:10 AM  
9:15 AM  
9:20 AM   Synthesizing a Concise, Exhaustive, Cost effective Accelerated Validation Plan.

Alexander (Alex) J. Porter  Engineering Development Manager 

Intertek ETL Entela
9:25 AM  
9:30 AM  
9:35 AM  
9:40 AM Environment and Usage Monitoring of Electronic Products for Health (Reliability) Assessment and Product Design

 Nikhil Vichare, Peter Rodgers, Valerie Eveloy, and Michael G. Pecht

CALCE Electronic Products and Systems Center, University of Maryland

  
9:45 AM  
9:50 AM Panel Discussion Paul Parker -  Power Supply Discussion
9:55 AM  
10:00 AM   Morning Break    Morning Break 
10:05 AM    
10:10 AM    
10:15 AM Case Study Accelerated Serviceability Stress Test (ASST)

 Karthik Balasubmaranian

Whirlpool Crop.

 Case Study Curvature measurements on PCB : experimental set-up and application for acoustical excitation 

François Lafleur, P. Eng., Ph.D.

CRIQ, Montréal, Canada 
10:20 AM Morning Break 
10:25 AM
10:30 AM
10:35 AM Heat Sink Fouling in Air-Cooled Electronics

 Aharon Nabi, Peter Rodgers, Avram Bar-Cohen

CALCE Electronic Products and Systems Center, University of Maryland
10:40 AM
10:45 AM
10:50 AM CASE STUDY  

Melissa Abuel

 HAT Process


Daniel Goulet 
10:55 AM
11:00 AM
11:05 AM
11:10 AM
11:15 AM Test Methodology To Determine Durability Of Interconnects Under Board Level Drop Testing Conditions

Joseph Varghese, and Abhijit Dasgupta

University of Maryland
11:20 AM
11:25 AM Utilizing AST as a comprehensive approach for bringing product to market. 

Mike Wells

Intertek ETL Entela

 Application of Accelerated Testing Techniques to Enhance Reliability andDurability of the DoD Identification Smartcard

John Fessler 
11:30 AM
11:35 AM
11:40 AM
11:45 AM
11:50 AM
11:55 AM  

Introduction to Cisco Video

Dennis Pachucki
12:00 PM      
12:05 PM   Cisco Video   Lunch   Lunch
12:10 PM    
12:15 PM    
12:20 PM    
12:25 PM    
12:30 PM Lunch   Committee Meeting    How to come up with a presentation

Eve Mattingley-Hannigan, TEST Engineering & Management

and

Alex Porter, Intertek ETL Entela
12:35 PM    
12:40 PM    
12:45 PM    
12:50 PM    
12:55 PM    
1:00 PM Tutorial   Components / Lead Free Lead free key note - Darvin Edwards Case Study  Nate Drees

Dell Inc.
1:05 PM  
1:10 PM Accelerated Life Testing (Alt) In Micro- And Opto-Electronics:  Its Role, Attributes, Challenges, Pitfalls, And Interaction With Product Development And Qualification Tests
1:15 PM
1:20 PM
1:25 PM
1:30 PM  
1:35 PM Dr. Ephraim Suhir HALT & HASS: Software Faults

Donovan Johnson

Allied Telesyn Research NZ Ltd.
1:40 PM  
1:45 PM University of California and
Nanoconduction Inc		 Dielectric Integrity Test for Flip-Chip Devices with Cu/Low-k Interconnects

Charles Odegard, Tz-Cheng Chiu, Cheryl Hartfield, Vish Sundararaman

Texas Instruments Incorporated, Dallas, Texas
1:50 PM
1:55 PM  
2:00 PM  
2:05 PM   Equipment Random Vibration Kurtosis Control

John Van Baren, President

Vibration Research Corporation
2:10 PM  
2:15 PM  
2:20 PM  
2:25 PM  
2:30 PM   Afternoon Break
2:35 PM  
2:40 PM   Afternoon Break
2:45 PM   Afternoon Break Reliability Evaluation of Printer Lead Free PCBAs 

Aamir Kazi

Dell Reliability Engineering,
Pratap Singh, RAMP Inc. 
2:50 PM
2:55 PM Charles Felkins, Principle Design Engineer

QualMark
3:00 PM
3:05 PM Tutorial  
3:10 PM Reliability Integration Across the Product Life Cycle
3:15 PM
3:20 PM  
3:25 PM Mike Silverman, CRE, Managing Partner
3:30 PM   Utilizing Reliability Testing to Overcome Pb-Free Assembly Challenges

Randy Schueller

Dell Component Engineering Manager Mechanical Group  

 Alternative Metrics for Random Vibration Testing

Gilbert Bastien, MSME, P.E. 

Screening Systems, Inc 
3:35 PM Ops A La Carte, LLC
3:40 PM  
3:45 PM  
3:50 PM  
3:55 PM  
4:00 PM  
4:05 PM Case Study COTS Parts and HALT as Applied to the Tactical Tomahawk Missile

Terry Tracy, Senior Principal Engineer

Honors Raytheon Missile Systems

 New Technology in Vibration for AST

 Gregg K. Hobbs, Ph.D., P.E.  
4:10 PM
4:15 PM Case Study The Fiber Menace – Dust testing in the 21st century

Dave Rahe

Professional Testing (PTI)
4:20 PM
4:25 PM
4:30 PM
4:35 PM
4:40 PM   Closing
4:45 PM    
4:50 PM        
4:55 PM        
5:00 PM   Load buses for Dinner Cruise        
5:05 PM            
5:10 PM            
5:15 PM            
5:20 PM            
5:25 PM            
5:30 PM       Driskill Dinner    
5:45 PM            
6:00 PM           Committee Meeting Wrap-Up 
6:15 PM   Bus Leaves        
6:30 PM            
6:45 PM   DINNER CRUISE        
7:00 PM       Tour Bus Leaves     
8:00 PM       DELL Tour / Dinner