ASTR 2006 - San Francisco, California

ASTR 2006

Workshop on Accelerated Stress Testing & Reliability

Sponsored by the IEEE/CPMT ASTR Committee and Co-Sponsored by UC Santa Cruz

THE 2006 ASTR WORKSHOP WILL BE HELD

October 4 - 6, 2006

San Francisco, California

Fisherman's Wharf

SCHEDULE HAS NOW BEEN POSTED!

INDIVIDUAL CONFERENCE REGISTRATION:

Click here to register online (credit card registration only)

Click here for a mail-in registration form (for checks, money orders, etc)

Over the last few years, Accelerated Stress Testing (AST) has been embraced by an ever widening array of worldwide companies seeking to reconcile the need for the highest quality product with the necessary push for early time-to-market. The purpose of the AST Workshop is to share ideas on better ways of accelerating and detecting hidden defects, flaws, and weaknesses in electronic and electro-mechanical hardware that would result in failures during usage. These techniques are focused on testing electronic hardware to destruction limits and root cause investigation to determine the physics-of-failure. The goal of AST is to produce mature products at market introduction and, in making it robust, the product can be screened for manufacturing defects with high combined stresses (beyond end-use specifications) for shorter lengths of time.

Location	Accepted abstractss	Exhibitors	Past Presentations
Tutorials	Technical Sessions	Speakers Info	Past Workshops

Welcome to the ASTR Chairman’s Corner. This part of the website will serve to report on past activities and to inform on upcoming events.

I would like to personally invite you and your associates to participate in the 2006 ASTR workshop in San Francisco, CA. This committee is dedicated to communicating best practices of accelerated stress testing and reliability. We do this by hosting an annual three day interactive workshop located in a different area of the US each year. The committee members understand first hand the value ASTR brings to product development. (click here for more information about the ASTR workshop committee)

This year's workshop will be held at Sheraton Fisherman's Wharf in San Francisco, California.

2500 Mason Street, San Francisco, CA 94133

Ph: 415-627-6513 Fx: 415-989-9757

Driving Directions to the hotel

Transportation Options to/from the hotel

Fisherman's Wharf map

INDIVIDUAL HOTEL RESERVATIONS: Each individual guest must make their own reservations by Thursday, August 31, 2006.

HOTEL ONLINE REGISTRATION to book your hotel room at Sheraton Fisherman's Wharf and receive the discounted room rate of $135/night.

Or call 1-888-627-7024. You must identify yourself as a member of "Accelerated Stress Testing Reliability Conference" to receive the discounted room rate of $135/night.

The all day tutorial program will be held on the first day of the Workshop and features well respected experts sharing their experiences and hard learned lessons. Two parallel sessions, Basic AST and Advanced AST Subjects, will ensure that experienced practitioners as well as those who are just entering the field will find useful and interesting presentations.

TUTORIAL TOPICS:

Failure Analysis
Design of Experiments
AST Procedures
AST Equipment
Mechanical AST
Thermal AST
Overall AST planning and management
Reliability of component packaging and/or assembly and/or systems
AST for specific systems: optoelectronic packaging, rf devices
Reliability of specific systems
Emerging technologies and future systems, such as MCM, System in Packaging, microsystems, nanotechnologies, and their reliability
Other AST issues

The two day workshop program will present new and innovative Accelerated Stress Testing techniques in use today. Past workshops featured speakers discussing their accomplishments in providing accelerated reliability testing for a wide range of products as well as failure analysis techniques and data analysis.