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The
IEEE EMC Society
Distinguished Lecturer Program
The EMC Society's Distinguished Lecturer Program (DLP) provides speakers
on various aspects of electromagnetic compatibility for EMC Society chapter
meetings and similar functions. While presentations to groups outside of
the EMC Society and the IEEE are encouraged, the program is not intended
for national or international EMC symposiums, regional conventions, local
colloquiums, trade shows, or commercial seminars. Speaking engagement
arrangements are made by the benefiting organization directly with the
Distinguished Lecturer. Scheduling and minimum audience size are at the discretion
of the Lecturer.
Distinguished Lecturer Engagements are Subsidized
Each Distinguished Lecturer may present six subsidized or shared expense talks each year. The EMC Society will reimburse Distinguished Lecturer's travel expenses for approved speaking engagements up to a recommended limit of $1000 per engagement, but this is subject to negotiation and program budget constraints. (When travel expenses for any single trip will exceed this amount, the Lecturer must obtain prior approval before making travel arrangements.)
The EMC Society will reimburse current Distinguished Lecturers up to $1,250 for presentations to EMC Chapters located outside the DL's home continent. Since budget constraints permit few of these trips per year, each trip must be approved in advance by the Distinguished Lecturer Program chairman and the Society's Director of Member Services. (Re: EMCS BOD, 5 May 1997).
The VP for Member Services may approve an increased funding for Intra-Region, international DL travel (or in other special cases, not covered by the current DL Travel Policy), not to exceed a total of US$1,500 per engagement. Requests for increased funding shall be provided by the DL including due justification and the recommendation of the DL committee chair. Requests for increased funding must be submitted at least 30 days prior to the said engagement. The approval of the VP for Member Services must be obtained prior to finalizing lecture arrangements. The VP for Member Services shall report to the BoD in any such case no later than the following BoD meeting (Re: EMCS BOD, 17 August 2006) .
Sharing of expenses between the benefiting organization and the EMC Society is encouraged. For example, the benefiting organization could provide local transportation for the Lecturer, provide meals, etc. Benefiting organizations will please give credit to the "Electromagnetic Compatibility Society, Institute of Electrical and Electronics Engineers" in their newsletter or other announcements.
Scheduling a Distinguished Lecturer
1.
Review lecturer list below, then contact lecturer directly to
arrange for the engagement:
• Date, time, and location of the
engagement
• Name and affiliation of benefiting organization
• Estimated audience size and type (engineers? students?)
• Topic lecturer will present
• Discuss what logistical needs can be provided by the
benefiting organization (e.g., ground
transportation, meals, handout copying, video display projector, other shared
expenses, etc.)
• Principal benefiting organization contact.
2.
Include summary of talk to be presented and lecturer's bio in the
benefiting organization's newsletter or meeting announcement.
Selection of Distinguished Lecturers
The program consists of at least four Distinguished Lecturers, selected by the Program Chairman from written nominations or application from EMC Society members, and approved by the EMC Society Board of Directors. The term for each Distinguished Lecturer is two years. Currently all terms start and end at the turn of a calendar year. Selection is based on (1) professional competence and recognition of EMC expertise, (2) communication and presentation skills, (3) EMC topics, (4) contribution to a balanced program, and (5) recommendation of EMC Society members. Membership in the EMC Society's Distinguished Lecturer program shall not be used in the advertising of products or [consulting] services, nor for any non-approved presentations such as product or training seminars or trade shows. Distinguished Lecturers may not, as part of any DLP presentation, advertise, market, or offer for sale, any commercial product or service.
Distinguished Lecturers
Dr. Joungho Kim - Dr. Eric L. Bogatin - Dr. Alistair P. Duffy - Dr. Stephan Frei - Dr. Ji Chen -
Dr. Sergiu Radu - Dr. Tzong-Lin Wu
Professor
Director of Convergence Device and System Group
Department of Electrical & Computer Engineering
KAIST (Korea Advanced Institute of Science and Technology)
Daejon, Korea
Phone: 82-42-869-3458
Email: joungho@ee.kaist.ac.kr
Term : 2009-2010 |
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- EMC design of IC and package
We are facing considerably increased concerns on EMC issues of high performance integrated circuits, and automotive semiconductor devices. They emit significant amount of high frequency electromagnetic radiated and conducted emissions and are susceptible to external electromagnetic noises, suffering degradation of system performance and reliability. In this talk, novel design and analysis methodologies will be introduced to provide optimal design approaches by combining IC and package hierarchical designs of equalizer and PDN impedance. In addition, measurement results of IC and package co-design will be shown including RF circuits such as LNA and PA, and analog circuits such as PLL, DLL, OpAmp, and ADC.
Outline:
- Background: Increased concern at high performance IC and automotive semiconductors.
- Electromagnetic emission and susceptibility issues of IC and package
- IC and package co-design and analysis of EMC: hybrid equalizer and low impedance PDN
- Electromagnetic susceptibility study on RF circuits: LNA, PA
- Electromagnetic susceptibility study of analog circuits: OpAmp, DLL, PLL, and ADC
- EMC design issues of 3D IC based on TSV
- Conclusion
- Low Electromagnetic Noise Design of System-In-Package
In order to meet intensively growing needs of extremely small form-factor semiconductor system solutions with sufficiently low cost for high-density and multi-function mobile platforms, 3D SiP has become the most promising design approach. However, heavily populated integration of multiples chips in three dimensional stacking structures on a multi-layer substrate in the SiP, inevitably yields considerable problems of signal integrity and power integrity. In this talk, design and analysis approaches will be introduced with the considerations of the signal integrity, power integrity, and electromagnetic coupling at the high speed and low noise 3D SiP's. In addition, we will introduce design and text examples including RFID, DMB, ZigBee, and UWB SiP's.
Outline:
- Introduction
- EMC issues in high-density SiP design
- Signal and power integrity issues in SiP design
- Hybrid equalization designs and measurements
- Novel 3D clock distribution networks for SiP
- Chip-package noise couplings and suppressions in SiP
- Design and measurement of RFID, DMB, ZigBee, and UWB SiP's.
- Low Noise 3D IC design
- Conclusions.
- Power Integrity of IC and Package
Power supply noise by digital switching is becoming the major source of electromagnetic noise generation and coupling in semiconductor systems. It could be even more serious in 3D SiP and IC based on vertical TSV type interconnections for high-density and multi-function mobile multimedia, computing, and communication system platforms. In this talk, new modeling, design, and analysis approaches will be introduced with the consideration of the power integrity. The unique methods are based on simultaneous and hierarchical chip-package co-design and modeling in order to offer cost effective design solutions. In particular, we will shown novel design methods and test results including thin film capacitor and EBG structures to minimize the power supply noise generation and coupling.
Outline:
- Introduction
- Power integrity of IC
- Power integrity of package
- Modeling and analysis of hierarchical PDN
- Hierarchical decoupling and high dielectric thin film design
- Noise generation and coupling by via and PDN's
- EBG structure and suppression of SSN
- PDN effects on RF and analog circuits.
- PDN design issues in 3D IC based on TSV
- Conclusions.
Back to list of lecturers
- The Three Most Confusing Principles In Signal Integrity And How Not To Be Confused. The words we use often affect our intuition and how we think about concepts. In signal integrity we use some words either incorrectly or ambiguously and this confuses our intuition. In this lecture we look at three concepts at the heart of signal integrity problems: inductance, characteristic impedance and differential impedance. We look at why they are confusing and then the right way of using the terms to help feed our engineering intuition to help us solve signal integrity problems.
- The Ten Habits of Highly Successful Board Designers. You can’t learn everything you need to about signal integrity in one hour, or in one day or even in one week. But most engineers don’t have the time to spend weeks learning the field. If all you will ever spend studying signal integrity is one hour, this is the hour you should take. By leveraging just ten design habits described in this lecture, any engineer can dramatically improve the signal integrity performance of their high speed products.
- Separating Myth from Reality in Signal Integrity: This lecture introduces the idea of a myth and the principle that putting in the numbers is the way to separate myth from reality. We apply this method to three myth examples: the return current in a diff pair is in the second line, corners should be avoided in transmission lines, and FR4 won’t work at GHz speeds. We then explore in what cases the myth might be true and how you can answer your own “it depends” questions.
- From Bit Banger to Gigabit Guru: There are four problems which prevent interconnects from being transparent at GHz rates. By understanding their root cause and the principles behind them, the solutions to overcome these limitations are obvious. This lecture walks through the problems, the root causes and some of the design directions which enable multi giga bit per second signals in conventional interconnects.
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- How to Improve Correlation Between Lab and Full Car Measurements with EMC Computations
Improved measurement methods in automotive EMC can help to detect critical problems already in the early design process. Also numerical simulation methods promise to support with finding serious EMC problems in advance. Unfortunately with large structures like automobiles direct numerical approaches do not work any more. It is required to mix different methods with measurements to get useful results. This talk presents new measurement methods in automotive EMC and outlines the status of EMC computation in automobile industry. Special attention is given to the question how to combine measurements with computed results. Results and approaches might be interesting for any EMC engineer dealing with large systems.
Outline:
- New methods for component measurements
- Capacitive Voltage Measurement
- Time domain measurements
- EMC simulation for better correlation
- How the future of simulation can look like?
- Conclusion
- Electrostatic Discharges - Improving the Reproducibility
Electrostatic discharges attract more and more interest due to more sensitive electronic devices and higher quality demands. Especially on the system level it can be difficult to reach reproducible test results. Not only the environment can affect failure levels. Also specification gaps in the standards can lead to significant variations. Problems will be discussed and countermeasures will be proposed. Results from automotive industry will be show that can be generalized easily to other application fields.
Outline:
- Where and how can it happen?
- Introduction into ESD physics
- The automotive ESD process
- Important test standards
- Known and new reasons for test reproducibility problems
- What can be done?
- Simulation Methods for Signal Integrity of Automotive Bus Systems:
How to simulate the signal integrity of bus systems like CAN or FlexRay
Bus systems like CAN, LIN or FlexRay became the last years standard in nearly every automobile. The networks made many of the reached advances in the last years possible. To keep prices low standard automotive components like simple cables have to be used, that were not designed to fulfill the demands of high data transmission links. With increasing size of the bus system the signal integrity becomes more and more crucial. This talk points out how to model and simulate automotive bus systems on the physical layer in order to optimize the SI properties.
Outline:
- LIN, CAN, FlexRay - modern automotive bus systems
- Signal Integrity of bus systems
- VHDL-AMS as modeling language
- Modeling of multi-conductor transmission lines
- Modeling of common mode chokes and termination networks
- Model generation for bus transceivers
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Professor De Montfort University
Head of Division of Engineering
Principal Lecturer
3 Foxglove Close
Mountsorrel, Lounghborough
Leics, UK LE12 7GN
Tel 0116 257 7056
Email: apd@dmu.ac.uk
Or
Email: Alistair.duffy@ntlworld.com
Term: 2008 - 2009
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- Validation of computational electromagnetics. A main problem being addressed here is that, as EMC engineers, we have a sense of when a result is good (or a comparison of results is good) irrespective of how visually complex those results actually are. Quantification is easy when the results have a simple structure using simple distance measures, correlation, etc. This task is not easy when we are faced with graphs with many peaks and troughs and differing mean amplitude levels. Yet we still have a ‘by-eye’ ability to label the graphs as ‘good’ or ‘better than the last bunch’ or ‘not good enough’. Over the years, research has focused on trying to capture this human-centered approach in a simple computer based approach. This lecture looks at the problem, how people actually look at these graphs, how we categorize ‘good’ or ‘bad’, how this can be captured in a computer implementable method and what challenges this now poses.
- Structured cabling. Our offices, and increasingly our homes, are wrapped in twisted pair cabling. It often does not seem as innovative as optical fibre or wireless solutions, yet the cabling that is ostensibly the same that carried signals of a few tens of kilocycles in the early days of telephony is looking towards handling 40 or even 100 gigabits per second. This lecture is a window on how this, often overlooked, technology works, its history and the challenges for its future.
- Reverberation chambers. As a test facility, reverberation chambers have a lot to offer, they isolate the inside and outside worlds, they can simulate terrestrial propagation paths, they can illuminate test objects with very high strength electromagnetic fields and they are a cheaper option than fully anechoic chambers or open area test sites. However, they also have some drawbacks compared with other facilities, such as the lack of ability to take directional measurements. This lecture presents the operation of reverberation chambers and some of the tests that can be performed in the chamber.
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Associate Professor
Department of Electrical & Computer Engineering
University of Houston
Houston, TX 77204
713-743-4423
Email: ji.chen@mail.uh.edu
Term 2009-2010 |
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- EMC/EMI issues in biomedical engineering: This topic will discuss the interactions between electromagnetic devices and biomedical system. In particular, we will discuss the electromagnetic devices such as walk-through metal detectors and MRI RF coil in human subjects and implanted devices.
- EMC/EMI in wireless communications: The SAR and board-level electromagnetic modeling will be discussed in this talk.
- Developing nano-scale structures for EMC/EMI: In this talk, we will discuss the modeling and development of micro-leveled periodic structures for EMC applications.
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Principal Engineer,NCE
Sun Microsystems, Inc.
Electromagnetic Compatibility Design
220 Jefferson Drive, MS UMPK25-102
Menlo Park, CA 94025 - 1164
Phone: (650) 786 - 3465
E-mail: sergiu.radu@sun.com
Term 2009-2010 |
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Engineering Aspects of Electromagnetic Shielding
Every electronic equipment use some type of shielding, and from a theoretical
point of view, electromagnetic shielding is among the difficult areas of EMC.
The lecture is introducing basic shielding concepts, insisting on their practical
limitations, and presents the typical engineering problems associated with
shielding. Among the aspects discussed are the materials used for shielding,
chassis resonances, shielding integrity problems (seams, joints, apertures,
perf patterns), aperture coupling and shield's grounding.
Outline:
1. Introduction: Electric, Magnetic and Electromagnetic shielding
2. Basics approaches to shielding: field theory (Kaden) and circuit theory (Schelkunoff)
3. Limits of the theoretical approaches: numerical simulations
4. Practical aspects of shielding, typical requirements, grounding scheme
5. Shield material: metal, plastic, typical coatings
6. Shield construction: rivets, joints, seams, apertures
7. Shielding and thermal issues: holes, perf patterns, honeycomb
8. Shield integrity and gaskets
9. Internal compartmentalization of a chassis, resonances
10. Practical aspects of source - aperture coupling
11. Shielding for radiated emissions, radiated immunity and ESD - reciprocity aspects and limits
12. Evaluation of shielding effectiveness
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An Overview of Chip Level EMC Problems
The CPUs and the VLSI chips are the primary sources of electromagnetic noise in
all electronic equipments. Reducing the electromagnetic noise at source level is
usually the best and the most economical solution. The lecture presents typical
interference mechanisms associated with CPU/VLSI, as well as mitigation methods
at die-level and package level. Among the aspects discussed are some power distribution
issues, on-die decoupling, package capacitors, routing aspects, the impact of back-bias
and forward-bias, and the impact of die-shrinks on the EMI performance of the VLSI chips.
Outline:
1. Introduction: typical CPU radiation
2. EMI mechanisms for VLSI chips
3. Heatsink effect for large chips
4. Power distribution effects for large chips
5. Package level design for EMI and SI
6. Package stack-up and layer allocation
7. Package capacitors and their effect, package resonances
8. Routing and pin allocation aspects
9. Die level - general aspects
10. On-die decoupling
11. Back-bias impact on EMI
12. Die-shrink impact on EMI
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Engineering Aspects of PCB Level EMC Design
The PCB design is a complex cooperation between electrical, mechanical, thermal, SI,
PI and EMC design. In a practical design, the EMC design engineer has to make trade-offs and understand the relative impact of different design choices. The lecture is an overview of the typical PCB design aspects and their role for the EMC performance. Among the aspects discussed are placement, stack-up, routing, decoupling, and grounding aspects. The design of the I/O ports , in order to pass the emissions and immunity tests is also discussed in greater detail.
Outline:
1. Introduction - what matters for EMI
2. Stack-up principles and practical examples
3. Placement - potential EMI impact
4. Routing aspects which may impact EMI
5. Decoupling: power engineering, SI and EMI approaches.
6. Grounding scheme and exceptions, heatsink grounding
7. Stitching
8. Spread spectrum use and limits
9. Ethernet port
10. USB port
11. Serial port
12. Serial buses (PCIe, SAS/SATA, IB) and EMI impact
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Professor National Taiwan University
Department of Electrical Engineering
1, Sec. 4, Roosevelt Rd.
Taipei, Taiwan R.O.C. 10617
Tel 886 2 33663690
Email: wtl@cc.ee.ntu.edu.tw
Term: 2008 - 2009
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- Signal integrity and link path design for high-speed circuits
- Power integrity issues and possible solutions in high-speed package
- Efficient modeling of the interaction of power distribution network of package and PCB
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For more information, contact the program chairman:
Bruce Archambeault, Ph.D.
IBM Distinguished Engineer, IEEE Fellow
EMC CoC
919-486-0120
t/l 526-0120
IBM
B306, E114
3039 Cornwallis Rd
Dept 18DA
RTP, NC 27709
barch@us.ibm.com
How to Become an IEEE EMC Society Distinguished
Lecturer
Previous IEEE EMC Society Distinguished Lecturers
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