MIPS VHDL Synthesis Models

A total of six VHDL source modules are used in the MIPS Model. TOP_SPIM.VHD is the top level of the hierarchy. IFETCH.VHD is the instruction fetch unit. IDECODE.VHD is the register file. CONTROL.VHD is the control unit. EXECUTE.VHD contains the data and branch address ALUs. DMEMORY.VHD contains data memory. The sub modules correspond to the different pipeline stages for the MIPS.

The following models are available

MIPSWVO.ZIP - For Viewlogic's Workview Office Tool. Install the files and run the VHDL synthesis tool. Click here for instructions or read the TOP_SPIM2.doc file in the zip file for details on running the tools.

MIPSALT.ZIP - For Altera's MAX PLUS II CAD Tool. Install the files then compile and simulate TOP_SPIM.

MIPSSYN.TAR - For the Synopsys Unix based CAD Tool. Source files in Unix tar file format. Untar files to a directory named mips. Vhdlan *.vhd files then use "vhdldbx -i SPIM.scr SPIM" to run simulation. MIPS.cs is a synthesis batch file.

MIPSWVP.ZIP - For Viewlogic's older Powerview, Workview, and Workview Plus Tool. Does not use IEEE Std Logic 1164. Viewlogic specific function calls are used for adders and FFs. Click here for instructions or read the TOP_SPIM.doc file in the zip file for details on running the tools.

For other CAD Tools that support VHDL IEEE Standard Logic 1164 only minor changes should be needed. Typically this is limited to different library and use statements at the beginning of each module. To port to another system, start with the *.VHD files from MIPSWVO.ZIP and check your CAD tool documentation to see which libraries your VHDL compiler requires.

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