HDL Tools

HDL Tools

SUBDESIGN PIO( bus_out[7..0] : BIDIR;)

VARIABLE

data_reg[7..0] : DFFE;

BEGIN

data_reg[].clk = strobe;

data_reg[7..0].ena= (pp_cmd[] == LD_DATA);

Visual State Diagrams

Altera PLD HDL Tools

Topics Menu

Menu

Previous slide

Next slide

Back to the first slide

View Graphic Version