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Abstract -
While industry and academia have been aware of the need for an
intensive study of embedded digital system design, resource constraints,
fuzzy objectives, and short-time horizon have handicapped progress.
The $150M Rapid Prototyping of Application Specific
Signal Processors (RASSP) program is a major DARPA/Tri-Service
effort designed to overcome these limitations <http://rassp.scra.org>.
This effort has developed a number of new technologies that will
lead to dramatically shorter prototyping times and reduced life
cycle costs. In an effort to ensure the successful transfer of
these new technologies, the RASSP Education & Facilitation
(RASSP E&F) program is working to transfer this technology
into graduate and undergraduate curricula by developing and transferring
educational material. Only by successfully inserting these rapid-prototyping
technologies into the curricula and research activities of the
university community will the long term benefits of these technologies
be realized. To achieve this technology transfer objective, the
RASSP E&F program has developed educational material on the
key elements of rapid-prototyping of embedded digital systems
technology. The result of this effort is a set of educational
"modules" covering selected topics. A module is designed
to cover a complete topic area and consists of approximately three
hours of lecture material in the form of completely prepared and
annotated slides, homework problems with solutions, laboratory
exercises and instructor's notes. In conjunction with IEEE, several
of the modules developed by the RASSP E&F program designed
to teach students the VHDL language were converted to HTML and
linked with the VHDL language reference manual to form a self-paced
VHDL Interactive Tutorial. A demonstration version of this
learning tool, currently published by IEEE, is presented.
The academic community is faced with three interrelated events
which require dramatic changes in the educational process in order
to meet our educational objectives. These events are necessitating
a paradigm shift. The first event is the ever increasing rate
of technological change. A 1996 study by the National Academy
of Engineering cites statistics which illuminate the problem of
how quickly technologies and knowledge bases are changing, "for
mechanical engineering the estimated half-life of knowledge was
cited as 7.5 years, for electrical engineering 5 years, and for
software engineering 2.5 years" [NAE96]. The second event
is the move from a local, industrial-driven economy, to a global,
technology-driven economy. As a result of this second event, those
economies that have a workforce trained in state-of-the-art technologies
will have a competitive edge in the next millennium and therefore
enable a high standard of living. The third and final event is
the shrinking budgets available for higher education. The confluence
of these events highlights the need to more effectively and efficiently
transfer advanced technological developments into practice via
our education system. This need for educators to do more with
less is widely understood [Tuc91, Dir95, Pet97].
The problem described above is particularly evidenced in the area
of electronic systems design and electronic systems design automation.
Through research and development activities like the $150M DARPA/Tri-Service
Rapid Prototyping of Application Specific
Signal Processors (RASSP) program, dramatic technological
advances are being made [Ric97]. In RASSP, these advances are
being driven by the objective to reduce design time and cost for
multi-board, embedded digital signal processing systems by a factor
of 4x while simultaneously improving quality. To realize the benefits
of activities such as RASSP, the technological advances must be
broadly disseminated, understood and applied.
In the case of RASSP, DARPA recognized that only by successfully
inserting these new technologies into the curricula and research
activities of the university community would the long term benefits
of those technologies be realized. To accomplish this, DARPA initiated
a ground breaking effort explicitly funded to transfer the RASSP
technology to the academic and industrial communities. This ground
breaking effort is the RASSP Education & Facilitation (RASSP
E&F) program.
The RASSP E&F program is working with small and medium size
universities to incorporate these new technologies into their
undergraduate and graduate curricula [Gad96]. To achieve this
technology transfer objective, the RASSP E&F program has developed
educational material on the key elements of rapid-prototyping
of embedded digital systems technology. The result of this effort
is a set of educational "modules" covering selected
topics. A module is designed to cover a complete topic area and
consists of approximately three hours of lecture material in the
form of completely prepared and annotated slides, homework problems
with solutions, laboratory exercises and instructor's notes. The
key strengths of this approach are two-fold. First, the approach
is modular, so that academic programs can incorporate only those
technological developments appropriate to their curriculum. Second,
the approach supports the continuous updating and sharing of educational
material by providing a mechanism for documenting research results
in a reusable, teachable form. Together, these strengths allow
educational material to be continuously upgraded facilitating
the efficient insertion of the latest technological advances into
university curricula. In addition, they provide the ability for
all participants in the research and education areas to leverage
each other. In conjunction with IEEE, several of the modules developed
by the RASSP E&F program designed to teach students the VHDL
language were converted to HTML and linked with the VHDL Language
Reference Manual (VHDL LRM) [IEE93] to form a self-paced VHDL
Interactive Tutorial [Gad97].
This paper is organized as follows. The modular educational approach
designed by the RASSP E&F team to facilitate the successful
transfer of new technologies and associated tools into the university
curricula is presented in Section II. The efforts to develop an
interactive tutorial are then presented and the key attributes
of the IEEE VHDL Interactive Tutorial discussed in Section
III. Section IV presents potential future directions for this activity.
Section V provides a brief conclusion.
The RASSP E&F team has developed a novel module-based framework
that can be used to efficiently insert the technology being generated
on the RASSP program into university and professional education
courses. Similar to the knowledge unit concept proposed by the
Joint Curriculum Task force [ACM91], modules are developed on
specific topics and used to develop or update courses. The attractiveness
of this approach is that it is easy to insert new material into
an existing course through the use of a module. Likewise, it is
easy to develop a new course that is customized towards a specific
set of goals by grouping together a collection of modules. These
capabilities are extremely useful in overcoming the traditional
difficulty that instructors have in inserting new material into
existing courses or changing the curricula to add new courses.
There are many advantages to encapsulating a focused amount of
material in a modular fashion:
By enabling the timely insertion of new technology into the classroom,
the module concept proves an essential element in addressing the
current issues addressing our higher-educational system. This
need is noted by the National Academy of Engineering which argues
for an educational system that is relevant to the needs of the
community [NAE95].
To accomplish this it is important to recognize the distinction
between science and engineering. Science is generally based on
experimental methods that allow the formulation of general theoretical
constructs. Applied sciences focus scientific theory to purposeful
activity. Technology and engineering, on the other hand, put applied
science to work efficiently in a process context. While science
seeks basic understanding, technology and engineering are primarily
goal-oriented activities in response to societal needs [Fre89,Lew93].
To ensure that the educational modules developed by the RASSP
E&F team meet the needs of engineering and specifically electronic
system designers, the RASSP E&F team has developed the concept
of an Educational Maturity Model or EMM. The EMM is important
because it provides the theoretical basis for determining a module's
content and organization [Mad97]. The EMM, developed by the RASSP
E&F team, has been derived from Bloom's taxonomy [Blo56].
The EMM concept and its relationship to the RASSP module content
and structure are presented next.
Derived from Bloom's taxonomy, the Educational Maturity Model
allows educational material to be classified according to the
levels defined below and illustrated in Figure 1.
The EMM suggests that Level 1 (basic) can be supported by typical
classroom instruction and presentation; Level 2 (applicative)
can be supported by hands-on laboratories that make use of point
tools (e.g., a VHDL simulator) to perform simple example problems;
Level 3 (deductive) can be supported by advanced hands-on labs
and notes or case studies describing the design of an advanced
subsystem(s), and the most advanced level; Level 4 (productive),
can be supported by material that allows the hands-on design and
prototyping of actual complex systems through the use of tools
and through evaluation of various tradeoffs. Level 4 educational
material prepares the student, with little additional on-site
training, for an immediate role as a productive engineer in industry
or government. Often a particular industry may hire engineers
educated to Level 3, and provide on-site courses to raise the
level of knowledge to Level 4. Level 4 does not stand alone but
requires "Level 3 understanding" in a number of related
areas of specialization, as it deals with aspects of the complete
system.
The Educational Maturity Model(EMM) allows organizations to develop
and evaluate training material at each of the levels. Currently,
very little is done in the typical university classroom beyond
Levels 1 and 2. Levels 3 and 4 are primarily outcomes of knowledge
gained in industry, and would greatly benefit the quality of education
in the engineering area were it included in the university curricula.
Cooperative industrial training, where the student spends summers
in industry, is often an attempt to substitute for Levels 3 and
4. In our efforts as part of the RASSP program, in addition to
Levels 1 and 2, we have attempted to ensure that the material
produced would support education at Levels 3 and 4.
A typical module structure, illustrated in Figure 2, consists
of three components. The first component is the fundamental theory
underlying the topic being covered. For example, in the module
on Test Technology, the theory includes a discussion of the test
problem, test generation and fault simulation theory, and design
for testability techniques. The second component consists of examples,
problems and case studies. This component provides simple examples
that illustrate the theory and provides problems that can be used
for homework exercises. The third component of a module is a hands-on
laboratory exercise. The laboratory exercise is intended to rigorously
demonstrate the concepts taught in the other sections of the module
by providing an opportunity to apply those theories on a significant
problem in a learn by doing fashion.
The relationship between course content and EMM level is presented
in Figure 3. Each module consists of a comprehensive discussion
of one technical sub area, (e. g., virtual prototyping) and presents
the technical details, examples, and case studies needed to obtain
a thorough understanding of the topic. Each module represents
a unit of a course that is independent of other modules in the
course (aside from prerequisite requirements). A typical module
is designed to provide three hours of lecture time.
As illustrated in Figure 2, a module provides Level 3 material
through detailed hands-on labs, and notes that describe actual
design projects (i.e., case studies). Level 4 is achieved through
a capstone design project that is a comprehensive hands-on top-down
design laboratory that covers the entire system design process
and spans several modules. It is important to note that
the material to support EMM levels 3 and 4 often requires collaboration
with an industrial partner. In the case of the RASSP E&F team,
Raytheon has provided significant industrial input as has Hughes,
Motorola, Lockheed Martin and others.
One of the major challenges in the development of the RASSP modules
was determining which modules should be developed. Initially,
a large list of topics that comprised the core of new RASSP technology
was prepared. These topics were then clustered into a few composite
areas of knowledge which represented candidate topics for modules.
Topics were selected based upon two criterion, which topics represented
the key technical contributions of the RASSP activity and that
background material which was necessary to understand the RASSP
activity and not generally available in today's university curricula.
Figure 4 illustrates the relationship between the RASSP top-down,
rapid prototyping design process and a comprehensive set of modules
that cover each phase of the RASSP system design process.
As described earlier, the module concept provides an instructor
with the flexibility of tailoring a course to meet a specific
goal by selecting appropriate modules and linking them to an appropriate
design project. In addition, modules can be used by an instructor
to effectively and efficiently introduce new material into an
existing course by inserting selected modules into that course.
Figure 5 illustrates how courses can be formed from a number of
modules where some modules may be shared between two courses.
Both of these approaches described above for utilizing modules
have been implemented and tested in a variety of undergraduate
and graduate courses taught at the University of Virginia, the
Georgia Institute of Technology and the University of Cincinnati.
In these trials, a sequence of 8 - 10 modules augmented with a
comprehensive system-design laboratory at EMM Level 4, was used
to form a new quarter or semester university course.
To date, over 25 different modules have been developed. These modules
are available for educational purposes on the WWW at <http://rassp.scra.org>.
Over 80 universities ranging in size from small, primarily teaching
institutions, to large research universities have obtained modules
for use in their curriculum. Selected results from utilizing these
modules can be seen in papers published in the proceedings of the
IEEE International
Conference on Microelectronic Systems Education [MSE97].
This conference was organized using the model of the VLSI Educators
Workshops held by NSF in the '80s. Its purpose is to provide a forum
for educators to share experiences and techniques for introducing
the principals of modern digital system design concepts into the
academic curriculum.
The wide use of these modules is one measure of their utility and
flexibility. Another example of the flexibility of the module
concept is illustrated by the use of the modules developed by
the RASSP E&F team to develop an IEEE VHDL Interactive
Tutorial CD-ROM. This tool was developed based upon several
of the VHDL modules developed by the RASSP E&F team. The objective
was to provide a complete, user-friendly reference to the VHDL
language which is an important part of a top-down, rapid-prototyping
electronic system design process. This CD contains a hyper-linked
version of the VHDL LRM integrated with hyper-linked versions
of the VHDL modules described above. The process for selecting
and converting modules to a multi-media form is discussed next.
The current curricula for digital system design was developed
in the early 1980's with the onset of the silicon revolution.
The focus has been on the design of products that are relatively
simple and inflexible in application, and can be rapidly realized
out of simpler hardware building blocks and implemented using
VLSI technology [Cas95]. These designs require very little software
beyond that for simple setup and control. In the current paradigm,
there is little link between advanced theoretical algorithms designed
within laboratories and their final implementation to meet an
application-specific need. The curricula of the early 1980's reflected
the level of digital design complexity of the late 1970's. At
that time the need for shorter design times, the need for hardware/software
co-design, and life cycle cost issues, brought on by increasing
design complexity, had not become apparent.
However, by the late eighties, the tremendous advances in electronics
manufacturing technology and concomitant increase in the complexity
and capability of the embedded digital systems used in the "smart"
products being sold indicated that the educational modus operandi
needed to be adapted. For example, the application of theory in
the form of hands-on design through labs was being advocated by
Denning, et. al. [Den89]. The report Computing Curricula 1991
[ACM91] proposed that rigid programs be made more flexible and
sensitive to individual goals. This report proposes the use of
"knowledge units" which contain a discrete amount of
related topical information to achieve these objectives.
The need to update the existing curricula is further evidenced
by a recent survey sponsored by Texas Instruments and Toshiba.
The results of this survey, designed to assess the status of hardware
description language (HDL) education in engineering schools within
universities in the United States and Japan [VHD95], are summarized
in Table 1. Given the importance of top-down, language-based design
techniques to meet the design challenges brought about by the
rapid change in manufacturing capabilities, the results of this
survey are significant. Indeed, this survey stimulated Robert
Rozeboom, former VP of Texas Instruments, to say, "It's clear
there is a significant need, and therefore, opportunity to increase
the amount of training among undergraduate electrical engineering
students at major universities worldwide [Jai95]."
The results of the survey presented in Table 1 provided the rational
for development of a VHDL interactive tutorial that would leverage
the VHDL modules developed by the RASSP E&F team and be made
widely available by arranging for IEEE to publish and distribute
the result. The project officially began in the Fall of 1995.
In order to make the project manageable and to provide a sense
of continuity, only four modules were selected for conversion into
a multi-media form from the nineteen that were then available. The
RASSP E&F team felt that these modules provided the instructional material
necessary to provide a good understanding of the basic elements
and structures of VHDL.
A. Multi-Media Conversion
Three primary areas needed to be considered and issues resolved
in converting the four selected modules to a multi-media representation.
These areas included organization and visualization (or look and
feel), portability, and business issues. Each of these areas is
discussed next.
Organization and Visualization Considerations:
Providing a coherent look and feel to the VHDL Interactive Tutorial
was the most important consideration that drove the development.
The module lecture material (see Figure 3) was created in PowerPoint
™ format. At the time the project to develop an interactive
tutorial was initiated, HTML and the WWW were still in their infancy.
As a result, the modules had to be manually converted into HTML.
Because PowerPoint provided more flexibility in the positioning
of graphics and text, HTML tables were needed in many cases to
obtain a layout similar to that in the original PowerPoint slide.
When this was first proposed, issues of browser portability were
raised. However, for the benefit of the end-user, it was determined
that tables would be utilized in spite of the browser portability
issues. As the project proceeded, browser technology evolved and
this ceased to be an issue.
Including graphics in the interactive tutorial was another issue
which needed to be addressed. All the graphics had to be recreated
for the multi-media version of the modules because many of the
original graphics were not in color and because of the difficulty in getting
only the PowerPoint graphics into a GIF format. Conversion of
an entire slide, including text was considered. However, this
alternative was eliminated because in order to allow linking between
items in the GIF version of the PowerPoint slide, other GIF PowerPoint
slides and the VHDL LRM, an ISMAP with CGI was required. At the
time only server-side ISMAPs were supported. Because of the increased
cost to the resulting product that would arise from including
a server and the complexity for the end-user in having to install
and set-up a server, this approach was deemed unsatisfactory.
Conversion of the VHDL LRM to HTML was a much more straight forward
process, since it only involved ASCII text. The major obstacle
was providing navigation capabilities that allowed the large amount
of information in the LRM to be cleanly integrated with the educational
material in the modules. The hyper-linking capabilities provided
by HTML provided the mechanism for developing the desired integrated
environment. Utilizing these capabilities, a uniform navigation
paradigm was established that allowed users to easily move between
major components of the interactive tutorial.
Portability Considerations:
An important portability consideration was the physical characteristics
of an end-user's terminal. Given the wide range of resolution
and screen sizes available, consideration needed to be given to
maximizing readability while minimizing scrolling. It was decided
that an 800x600 default screen size provided the best display
over a wide range of screen resolutions and sizes. If real-time
scaling of pages were allowed, this would not have been a problem.
Another related consideration was text size. Since the default text size is
determined by the way the end user configures the browser,
it was necessary to select an assumed default setting and then
suggest that the user adjust their setting accordingly. Another
consideration that would affect the portability of the interactive
tutorial involved file naming conventions. Since the broadest
possible market was the target for this interactive tutorial,
the most general naming convention possible was adopted - ISO
9660. By using the ISO naming convention, all existing operating
systems and machines architectures that supported WWW browsers
would be able to utilize the interactive tutorial.
Business Considerations:
To realize the objective of producing a self-paced interactive
tutorial that would be broadly available and address the problems
identified in Table 1, the business considerations were almost
as important as the technical considerations. The primary issue
involved protection and sharing of intellectual property. As we
move from a paper dominated mode of information/knowledge transfer
to electronic media, these business issues will continue to be
confronted. This concern was magnified by the fact that in creating
the Interactive Tutorial, information that had been available
only in paper form was being made available in not only an electronic,
but a network accessible form. As a result, special attention
had to be paid to ensuring that the copyright restrictions would
be observed.
The VHDL Interactive Tutorial consists of three major components,
the home page, the hyper-linked version of the VHDL LRM, and the
multi-media versions of the VHDL modules. A uniform navigation
paradigm was established that allows users to easily move between
major components of the interactive tutorial. This is illustrated
below:
A demonstration version of the VHDL Interactive Tutorial
is provided to demonstrate the features and capabilities of a
self-paced, interactive tutorial and associated navigational mechanisms. For more information
see <http://standards.ieee.org/catalog/cd.html>.
The VHDL Interactive Tutorial is being sold commercially
by the IEEE . The cost is similar to that for which the VHDL LRM
in paper form had previously been sold. Because of the complexity
of the VHDL language, an environment that allows users to quickly
find answers to language related questions where both the formal
definition and useful examples and explanations are available
makes the tutorial extremely effective. It can be used by those
first learning the VHDL language as a tutorial environment and also
by those already experienced in the language as a reference
environment. As a result, the response to the tutorial has been
universally positive.
In the following section, plans for extending the VHDL Interactive
Tutorial are presented and conclusions on the impact and potential
future directions of activities such as those described in this
paper are discussed.
As noted above, the community's response to the VHDL Interactive
Tutorial has been very positive. One of the desires of those
using the tutorial is that it be extended to include an actual
simulation environment. Such an extension would allow users to
seamlessly move between examples to "learn by doing"
through the solution of simple problems. In effect, the VHDL
Interactive Tutorial would be extended to include EMM level
3 as described previously.
With the cooperation of Mentor Graphics Corporation, the feasibility
of this concept has been tested through the development of a Web
based front-end for Mentor Graphics QuickHDL™ VHDL simulator.
By providing an HTML wrapper for a simulator it was possible to
demonstrate the interweaving of educational material in the form
of definitions, examples, simple problems and a VHDL execution
environment where end-users could click on an example and utilize
it as the basis for performing a simulation or using it as the
basis to solve a simple problem using the simulator.
The challenge that is faced in integrating a simulation environment
with the VHDL Interactive Tutorial is the impact on the
ubiquitous usage of the tutorial. Currently all that is needed
to utilize the VHDL Interactive Tutorial is a WWW browser
capable of supporting HTML 2.0 and up. Such browsers are freely
available for every platform and operating system.
The reason that a simulator was not included, is that at the time the tutorial
was created no VHDL simulator met the properties desired for the CD. That is
was freely available on a variety of platforms and operating systems, and
properly implemented VHDL 1076-1993. The RASSP E&F team is currently
considering the best way to satisfy the competing demands of embedding a
simulation capability into the VHDL Interactive Tutorial environment and
that of ubiquitous access.
A second desire that has come from those using the tutorial is
to expand its scope. As mentioned above, the current VHDL Interactive
Tutorial incorporates only four of over 25 modules developed
by the RASSP E&F team. Thus, the current instantiation of
the tutorial supports learning of the basic elements and constructs
of the VHDL language. Many of the benefits of its application
such as those recently demonstrated by the Lockheed Martin Advanced
Technology Laboratories RASSP program in which at least a ten-fold
reduction in software development time and a five-fold reduction
in integration and test time were achieved through the application
of the RASSP methodology [Zeb96] are not conveyed. In order to
provide a learning environment in which all of the benefits of
the RASSP methodology could be easily learned, all of the modules
developed by the RASSP E&F team would need to be integrated
into an Interactive Tutorial environment. Fortunately, although
the current VHDL Interactive Tutorial took considerable
effort to construct due to the immature nature of the WWW at the
time the project was started, the rapid maturation of Web technology
and tools would dramatically reduce the effort required to develop
the same tutorial today thus making a future version of the tutorial
that not only teaches the VHDL language but how to effectively
apply that language economically feasible.
The RASSP E&F project has been driven by the need to transfer
the RASSP information and methodologies into the academic and
industrial areas. The chances of insertion into these areas have been
greatly enhanced by the utilization of course modules and web
accessible information. This approach although demonstrated on
the RASSP technology is generally applicable to technology transfer.
The increasing rate of technological change noted by the National
Academy of Engineering [NAE96] presents tremendous challenges
for the educational community. It has been said that the only
sustainable competitive advantage is learning faster than your
competition. To the extent that this is true, our standard of
living depends on the effectiveness of our educational system.
Given the budget constraints impacting educational institutions,
the educational system must also be efficient. The module concept
is potentially an important component in a comprehensive solution
that meets these challenges. The establishment of a national repository
that can support the distribution, maintenance and updating of
educational modules is ultimately necessary to realize the potential
benefits associated with the module concept. The RASSP server
<http://rassp.scra.org> provides a mechanism for electronic
access and distribution of the modules developed by RASSP [Com96].
Extending this repository to include modules developed by other
educators and made available to the education community beyond
DARPA's funding for the RASSP program is a key objective of the
RASSP E&F team. Another objective is to establish a system
that will continuously evolve to improve the module concept. The
IEEE International
Conference on Microelectronic Systems Education
has been established to address some
of these issues by providing a forum for educators to share experiences
and techniques for introducing the principals of modern digital
system design concepts into the academic curriculum.
Integrating the module concept with the WWW to create a self-paced,
multi-media learning environment has proven that the integration
of these technologies can have significant benefits. The combination
of WWW delivery and modules can be the basis for the establishment
of the life-long-learning environment called for by the National
Academy of Engineering [NAE96].
The authors gratefully acknowledge the support from the Defense
Advanced Research Projects Agency Electronics Technology Office
(DARPA/ETO) and United States Air Force Wright Aeronautical Laboratory
under contract number F33615-94-C-1457 without whose support this
work would not have been possible.
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Anthony J. Gadient
Jack A. Stinson, Jr.
Tommy C. Taylor
James H. Aylor
Robert H. Klenke
Maximo H. Salinas
Vijay K. Madisetti
Thomas Egolf
Shahram Famorzadeh
Larry N. Karns
Harold W. Carter
Anthony J. Gadient is the Director of Research at the South
Carolina Research Authority in Charleston, South Carolina. He
received his Ph.D. in Electrical and Computer Engineering from
Carnegie Mellon University in 1992, an M.B.A. from Wright State
University in 1986 and a B.S.E.E. from the University of Virginia
in 1982. His research interests include environments for distributed
collaboration, distance learning, design tool interoperability
and rapid prototyping of embedded electro-mechanical systems.
In addition to his other responsibilities, Dr. Gadient is the
Principal Investigator for the RASSP Education and Facilitation
program and a senior member of the IEEE.
Jack A. Stinson is a Principal Engineer at SCRA with over
twenty years of industrial and academic engineering experience.
His work on the RASSP E&F program include managing an advanced
world wide web server and producing an Interactive VHDL tutorial
CD-ROM that is published by the IEEE. Dr. Stinson received his
Ph.D. and M.E. degrees in Electrical Engineering from the University
of South Carolina and his B.S. in Electrical Engineering from
Clemson University. He is also a registered professional engineer
in the state of South Carolina and a senior member of the IEEE.
Tommy C. Taylor is a Software Engineer in the Advanced
Technology Institute at the South Carolina Research Authority in Charleston,
South Carolina. Mr. Taylor's research interests include network
based applications and distributed programming. Mr. Taylor has
been involved with a wide array of developments applying advanced
Internet technologies to support distributed collaboration and
technology transfer. In addition, Mr. Taylor is the Webmaster
for the RASSP web-site, identified in IEEE Spectrum as one of
the top three web sites for digital signal processing information.
He received his BA in Computer Graphics from the College of Charleston.
James H. Aylor is a Professor and Chairman of the Department
of Electrical Engineering at the University of Virginia. . His
research interests include system level and hybrid modeling, hardware
description languages, performance level analysis, microelectromechanical
systems, and high speed digital design. Aylor received his B.S.,
M.S., and Ph.D. degrees, all in Electrical Engineering, from
the University of Virginia. Professor Aylor is a member of the
IEEE Computer Society and a Fellow of the IEEE.
Robert H. Klenke is currently a Principal Scientist in
the Center for Semicustom Integrated Systems at the University
of Virginia. His research interests include system level modeling,
hardware description languages, parallel algorithms for automatic
test pattern generation, and high speed digital design. Klenke
received his B.S. degree in Electrical Engineering from the Virginia
Military Institute in 1982, and his M.S. and Ph.D. Degrees in
Electrical Engineering from the University of Virginia in 1989
and 1993, respectively. He is a member of the IEEE Computer Society,
Tau Beta Pi, and Eta Kappa Nu.
Maximo H. Salinas is a member of the research staff of
the University of Virginia Center for Semicustom Integrated Systems
(CSIS). He received the B.S. degree from the Massachusetts Institute
of Technology in 1984 and the M.S. degree from the University
of Virginia in 1990, both in Electrical Engineering. He is currently
completing a Ph.D. in Electrical Engineering at the University
of Virginia on the modeling of computer instruction set architectures.
Mr. Salinas research interests include computer architecture,
digital design methodology development, and microelectromechanical
systems (MEMS). He is a member of Eta Kappa Nu, Tau Beta Pi, and
the IEEE Computer Society,
Vijay K. Madisetti received his Ph.D. from the University
of California at Berkeley in 1989. Dr. Madisetti is currently
an associate professor of electrical and computer engineering
at the Georgia Institute of Technology with interests in the areas
of rapid prototyping, digital systems design, and signal processing.
He is the author of the IEEE Press textbook, VLSI Digital Signal
Processors (1995), the Editor-in-Chief of CRC Press/IEEE Press
"Handbook of Digital Signal Processing" (1997), is the
Associate Editor of IEEE Transactions on Circuits and Systems,
and a member of the IEEE Computer Society.
Thomas Egolf received his B.S. in Electrical Engineering
from the University of Pittsburgh in 1983, his M.S. in Electrical
Engineering from Johns-Hopkins University Applied Physics Lab
in 1989 and is currently pursuing his Ph.D. at Georgia Institute
of Technology. His research interests include VLSI signal processing,
computer architectures for DSP, speech processing, and methods
for virtual prototyping of systems. He is currently working on
the Rapid Prototyping of Application Specific Signal Processors
(RASSP) program under contract from the Defense Advanced Research
Projects Administration. He is a member of the IEEE Signal Processing
Society and the IEEE Computer Society.
Shahram Famorzadeh is a Ph.D. candidate in the School of Electrical and
Computer Engineering at Georgia Institute of Technology. His research
interests include adaptive distributed signal processing, rapid prototyping
of electronic systems via HLL, and HW/SW codesign techniques for embedded
signal processors. Famorzadeh received a B.S.E.E. from University of
Tennessee at Knoxville, and an M.S.E.E from the Georgia Institute of
Technology in 1989 and 1990, respectively.
A. Educational Maturity Model (EMM)
B. Module Content and Structure
C. Modules and the RASSP Top-Down, Rapid Prototyping Design
Process
D. Results To Date
B. Overview of the VHDL Interactive Tutorial
Each slide consists of three primary elements, a title, a
lesson body and a tool bar. The tool bar provides
access to previous and next slides, previous and next sections,
to notes pages and to the map and index.
A picture of a typical module slide is presented next.
C. Summary
<http://rassp.scra.org/bios/gadient/index.html>
<http://rassp.scra.org>
<http://www.scra.org>
SCRA
5300 International Blvd.
Charleston, SC 29418
Phone: 803-760-3376
Fax: 803-760-3349
Email: gadient@scra.org
<http://rassp.scra.org/bios/stinson/index.html>
SCRA
5300 International Blvd.
Charleston, SC 29418
Phone: 803-760-3581
Fax: 803-760-3349
Email: stinson@scra.org
<http://rassp.scra.org/bios/taylor/index.html>
SCRA
5300 International Blvd.
Charleston, SC 29418
Phone: 803-760-3563
Fax: 803-760-3349
Email: taylor@scra.org
<http://rassp.scra.org/bios/aylor/index.html>
<http://csis.ee.virginia.edu/research/research.html>
Department of Electrical Engineering
Thornton Hall
University of Virginia
Charlottesville, VA 22903
Phone: 804-924-6100
Fax: 804-924-8818
Email: jha@virginia.edu
<http://rassp.scra.org/bios/klenke/index.html>
Department of Electrical Engineering
Thornton Hall
University of Virginia
Charlottesville, VA 22903
Phone: 804-924-6079
Fax: 804-924-8818
Email: klenke@virginia.edu
<http://rassp.scra.org/bios/salinas/index.html>
Department of Electrical Engineering
Thornton Hall
University of Virginia
Charlottesville, VA 22903
Phone: 804-924-6101
Fax: 804-924-8818
Email: msalinas@virginia.edu
<http://rassp.scra.org/bios/madisetti/index.html>
<http://www.ece.gatech.edu/main>
School of Electrical and Computer Engineering
Georgia Institute of Technology
777 Atlantic Drive.
Atlanta, GA 30332-0250
Phone: 404-894-4696
Fax: 404-894-4641
Email: vkm@ee.gatech.edu
<http://rassp.scra.org/bios/egolf/index.html>
School of Electrical and Computer Engineering
Georgia Institute of Technology
777 Atlantic Drive.
Atlanta, GA 30332-0250
Phone: 404-894-0860
Fax: 404-894-4641
Email: egolf@ee.gatech.edu
<http://rassp.scra.org/bios/shahram/index.html>
School of Electrical and Computer Engineering
Georgia Institute of Technology
777 Atlantic Drive.
Atlanta, GA 30332-0250
Phone: 404-894-0860
Fax: 404-894-4641
Email: shahram@ee.gatech.edu
<http://rassp.scra.org/bios/karns/index.html>
<http://www.scra.org/adl/ADL.html>
Arthur D. Little
5300 International Blvd.
Charleston, SC 29418
Phone: 803-760-3278
Fax: 803-760-3349
Email: karns@scra.org
<http://rassp.scra.org/bios/carter/index.html>
<http://www.uc.edu>
University of Cincinati
ECI Dept., Mail Location 30
Cincinnati, OH 45221-0030
Phone: 513-556-4781
Fax: 513-556-7326
Email: hal.carter@uc.edu