MOSFET : Threshold Voltage, ON-OFF and Linear-Saturation Behaviors

I. Threshold Voltage, V_T

An n-channel MOS transistor is fabricated on a p-type Si substrate. Its cross-sectional schematic is

image here .. n-channel

where the n⁺ regions are the Source and Drain of the transistor. When a gate voltage V_G, which is more positive than the threshold voltage V_T, is applied, sufficient amount of (negatively charged) electrons are gether under the Gate (in the surface region of Si), making a conducting path between the Source n⁺ region and the drain n⁺ region. The following applet shows this.

applet here ... VG changing, channel forming

A p-channel MOSFET is formed on an n-type Si, as the schematics show below.

image here .. for p-channel

For p-channel device, a gate voltage V_G, which is more negative than V_T, should be applied to have a positive-charge (hole) conducting channel formed under the gate.

The Gate material, gate oxide thickness, and the doping level in the semiconductor Si together determine the threshold voltage, V_T. Let us find VT in terms of the physical parameters of the transistor.

1. When the starting condition is a Flat Semiconductor Band

The formation of a conducting channel is entirely the business of Metal-Oxide-Si structure, and the presence of the source and drain regions play no role. Thus, we consider the MOS structure made on a p-type Si substrate (ie., n-channel device). Let us first assume that, without any applied gate bias, the semiconductor band diagram shows a flat band condition as shown below.

MOS image (to be drawn), and flat band image (xv of applet)...

Now, in the following applet, change VG (use the scrollbar) and observe the changes in charge density in the semiconductor, in the region right next to the gate oxide.

applet for the band diagram ... and the charge density ...

Since the Source and Drain regions are doped heavily with donors (ie, n+ type), only a negative-charge (ie, electron) conducting channel will complete a conducting path between S and D. Thus the inversion condition is for "ON" and both depletion and accumulation are for "OFF".

2. In real devices, the Semiconductor Band is Bent under zero gate bias

2.1 Contribution of the Work Function Difference

applets here ...

2.2 Contribution of the Oxide Charge

applets here ...

2.3 Correction to the VT by VFB

3. Threshold voltage

applet: VFB = PhiMS - Qo/Co, VT = VFB - Qb/Co + Phi.s.i. each term for gate material (Al, p-Poly, n-Poly), Oxide thickness and charge, and semiconductor doping (Na or Nd).

applet: Gate material selection, oxide thickness selection, doping type selection => VT vs. N => single or multiple plots.

II. Threshold Voltage Matching of a CMOS Inverter, a Design Question

III. Static Characteristics of the MOS Transistor