IEEE 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Return to Table of Contents


A PSpice Tutorial for Demonstrating Digital Logic

Michael G. Giesselmann, Senior Member, IEEE

Abstract - Several new features of the Evaluation version of PSpice are used to generate demonstration examples for teaching digital logic. An important innovation is the ability to display logic levels on the Schematics page for combinatorial logic circuits. Some of the other main features that are being explored in the examples are hierarchical structures and busses. The paper contains many actual screen views. All circuit files that are discussed in the paper, are included on the CD-ROM.

I. Introduction

At Texas Tech University, PSpice is being used throughout the Electrical Engineering Curriculum. Recent advances in the code, that make PSpice a completely integrated electronic design and analysis tool, and the availability of a free evaluation version make PSpice an ideal companion for the students throughout their progression in the curriculum. In the not so distant past, many different incompatible programs were used for different classes, i.e. PSpice for analog electronics, PCAD for circuit boards, B-squared logic for digital logic and Altera for programmable logic. With an integrated package like PSpice, the students can get in in-depth experience with a sophisticated, real world CAD tool. Since the students are exposed to PSpice in many classes in progressive order, they can learn many advanced techniques, which could not be covered, if they were only exposed to a program for one semester. The students are also rewarded in later classes for learning a program well, which is a rare experience in today's short lived commercial software environment, where the only constant seems to be ever shorter upgrade intervals. In addition, a very in depth knowledge of PSpice will be easily portable to other major electronic design environments like Saber etc., which are all structured similarly.

Another important goal, which requires in-depth knowledge is to teach not only the capabilities of a software package, but also the underlying models and limitations, and to teach the proper use of such a tool.

The PSpice schematics editor provides a very powerful and easy to use interface to generate digital circuits. Some of the main features that are being explored in the examples are hierarchical structures and busses, and bias voltage display. Hierarchical structures enable the student to create structured designs with sub-circuits at several levels. Busses are essential to un-clutter the often numerous connections between digital circuits. Bias point display creates the ability to see the results of a simulation of combinatorial logic directly on the screen.

II. Simulation of Combinatorial Circuits

Figure 1 shows a screen-view of the Schematics editor showing all possible input combinations of AND, OR, NAND, NOR, and EXOR gates with two inputs (Filename=Gates.sch). The result of the simulation is directly displayed in the Schematics page after clicking first on the Bias Point Calculation Button and turning on the bias point display.

Figure 1: Schematics screen view showing AND, OR, NAND, NOR, and EXOR gates with termination sub-circuits and logical Bias levels displayed.

In order to force PSpice to perform a Bias point calculation, analog elements need to be inserted into the circuit. This will cause PSpice to add Digital to Analog interface circuits into the netlist. However, these Interface circuits are not shown. The bias point is the starting (DC) initial value of a transient circuit simulation. The resistors shown in Figure 2 (Filename=Term_4.sch) perform this function. However, if the outputs of the gates under investigation were directly terminated with resistors, the Bias Point display would show actual voltage levels instead of the logic levels shown in Figure 1. In order to force PSpice to show Logic levels, the open collector drivers shown in Figure 2 are used.

Figure 2: Termination circuit for logic level display using Bias point calculation.

The logic inputs of the 7407 drivers forces the display of logic levels rather than analog voltage values. During the simulation, the schematic diagram is being translated into a netlist which is passed on to PSpice for simulation. During this process, Analog to Digital interfaces are being inserted between the output of the open collector drivers, and the 10kW pull-up resistors. The complete sub-circuit shown in Figure 2 resides in the hierarchical blocks Term_4x shown in Figure 1.

Figure 3 shows an example of using a more complex circuit like an MSI full adder in a add-subtract circuit and displaying the results directly in Schematics. In Figure 3, (Filename= Add_sub.sch), the circuit on the left is adding two 4-bit binary numbers with Mode=0, whereas the circuit on the right is subtracting the same two 4-bit binary numbers with Mode=1.

Figure 3: Schematics screen view showing Add-Subtract circuit using an MSI adder with termination sub-circuits and logical Bias levels displayed.

Finally, the most complex example provided for combinatorial logic is shown in Figure 4. Here the hardware for a complete 4x4 binary multiplier (Filename= 4x4_mult.sch) is shown. Here six MSI 7483 full adders along with additions logic are used. In order to enable the Bias point calculation and assure the display of logic levels, two terminators like the ones shown in Figure 2 are used. Again, the results of the simulation; the logic levels at all places are directly shown on the Schematics page.

III. Simulation of Sequential Circuits

The analysis of sequential circuits, i.e. Circuits with Flip-Flops must be performed in the time domain of course. Typical basic circuits are counters and shift registers. The first example on sequential logic shows a circuit using a 74160 and a 74162 synchronous decade counter (Filename=160_162.sch).

Figure 4: Schematics screen view showing 4x4 bit multiplier circuit using an MSI adder with termination sub- circuits and logical Bias levels displayed.

Figure 5: Schematics screen view showing 2 synchronous counters with premature reset showing the difference between synchronous and a-synchronous reset.

The difference between the devices is that the 74160 has a asynchronous reset, whereas the 74162 has a synchronous reset. A screen view of the circuit is shown in Figure 5. The asynchronous reset is immediate except for the propagation delay whereas the synchronous reset will be effective at the next positive edge transition of the clock. The result is that with the identical reset circuitry shown in Figure 5, the counter with the asynchronous reset will only count to 5 whereas the counter with the synchronous reset will count to 6. This is shown in the output diagram taken from the Probe post-processor in Figure 6. Note, that the use of a bus for the output of the counter and the placement of a Voltage/Level Marker on the bus will automatically instruct Probe, to represent the result of the count in Hexadecimal form. This is done by an alternate way of data representation and does not require the storage of additional data in the output data file.

Figure 6: Probe screen view showing 2 synchronous counters with premature reset showing the difference between synchronous and asynchronous reset.

Figure 7: Schematics screen view showing top level of 4-bit ripple counter.

The next example shows a 4-bit ripple counter with hierarchical blocks, which expand to JK flip-flop circuits. Figure 7 (Filename=4bit_rip.sch) shows the top level view of the circuit. The second hierarchical JK-Flip-Flop block is selected. Upon double-clicking, it reveals the underlying flip-flop circuit shown in Figure 8 (Filename=JK.sch).

Figure 8: Schematics screen view of JK flip-flop implementation.

The circuit shown in Figure 8 is contained in the file named JK_FF.sch. Only one instance of this file is needed and all four hierarchical blocks shown in Figure 7 refer to the same file. The input/output ports shown in Figure 8 on the left and right side respectively, are called interface ports. These ports connect to the identical named terminals in the hierarchical blocks shown in Figure 7. Figure 9 shows the output of the ripple counter with individual traces and a combined Hexadecimal representation of the output bus. Figure 10 shows the same result of the ripple counter simulation, but with an expanded time scale at the position were the transition between count 7 and 8 takes place. This Figure clearly shows the ripple effect of consecutive flip-flop transitions that give this counter his name.

Figure 9: Output of Ripple Counter with individual traces and combined bus signal.

Figure 10: Output of Ripple Counter with expanded time scale around the transition between count 7 and 8.

Conclusions

This paper has shown, how some of the new features of the Evaluation version of PSpice can be used to simulate digital circuits. One of the salient new features is the Bias point display on the Schematics page, which greatly enhances the treatment of combinatorial Logic. This feature is specifically appreciated by students in a first course on Digital Logic. In the past the students have often been confused about the necessity to perform transient analyses to obtain simulation results of combinatorial circuits. Some of the other main features that are being explored in the examples are hierarchical structures and busses.

References

PSpice Manual Library, Release 8.0, MicroSim Corporation, Irvine, Ca, 92718. Website: http:// microsim.com.

Author Contact Information

Michael G. Giesselmann, http://www.ee.ttu.edu/ee/giesselm.htm.

Department of Electrical Engineering

Texas Tech University, Lubbock, Texas 79409.

Phone: 806-742-3462

FAX: 806-742-1281

E-Mail: MichaelG@coe.ttu.edu.

Author Biography

Michael G. Giesselmann, biography. Michael Giesselmann was born in 1956 in Basel / Switzerland. After school he studied Electrical Engineering at the Technical University of Darmstadt (TUD)/Germany from 1975-1981. From 1981-1986 he worked as a research assistant at TUD and received a Doctoral degree in Electrical Engineering in 1986. In 1986 Dr. Giesselmann joint the faculty of the EE department at Texas Tech University. He is a Senior Member of the IEEE and a member of the Power Electronics Society, the Power Engineering Society, the Industry Applications Society and the Industrial Electronics Society. Within the Industry Applications Society, he is a member of both the Industrial Drives and the Electric Machines Committee. Dr. Giesselmann is very involved and interested in using information age technology in the classroom. He received the University President’s Excellence in Teaching Award in 1995 and is a Charter Member and Executive Council Member of the TTU Teaching Academy since 1997.

 

Return to Table of Contents