Design, Implementation and On-Chip High-Speed
Test of SFQ Half-Precision Floating-Point Multiplier

H. Hara, K. Obata, H. Park,Y. Yamanashi,K. Taketomi,
N. Yoshikawa M. Tanaka, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa

Abstract—We developed a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm² Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm × 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

Index Terms— floating point units, LSRDP, multiplier, SFQ circuits, superconducting integrated circuits

Manuscript received 19 August 2008.
This research was supported by CREST, Japan Science and Technology Agency.
H. Hara, H. Park, Y. Yamanashi, K. Taketomi and N. Yoshikawa are with the Department of Electrical and Computer Engineering, Yokohama National University, Yokohama, 240-8501 Japan. (phone: +81-45-339-4269; fax: +81-45-339-4269; e-mail: hara@yoshilab.dnj.ynu.ac.jp).
K. Obata, M. Tanaka, N. Takagi and K. Takagi are with the Department of Information Engineering, Nagoya University, Nagoya, 464-8603 Japan.
A. Fujimaki is with the Department of Quantum Engineering, Nagoya University, Nagoya, 464-8603 Japan. S. Nagasawa is with ISTEC-SRL, Tsukuba, 305-8501 Japan.

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