Welcome to the 17th IEEE International Memory Workshop
May 18th-21st 2025 in Monterey, CA, USA
Monterey

The 17th IEEE International Memory Workshop (IEEE IMW) will be held in 2025 in Monterey. It is currently planned as an on-site event. This conference brings the memory community together in a workshop environment to discuss the memory process and design technologies, applications, market needs and strategies. It is sponsored by the IEEE Electron Devices Society and meets annually in May.

Although it is the 17th IMW meeting to be held next year, it has a long history of Non-Volatile Semiconductor Memory Workshops (NVSMW) dating back to 1976. In 2008, NVSMW and the International Conference on Memory Technology and Design (ICMTD) merged to incorporate both the volatile and non-volatile memory aspects in one forum while maintaining the workshop experience. And the scope was extended from non-volatile memory technology and design, which had been successfully discussed in more than 30 years of NVSMW, to the other memory technologies, which were the focus of ICMTD.

The IEEE IMW is the premier international forum for both new and seasoned technologists having diverse technical backgrounds to share and learn about the latest developments in memory technology with the global community. The scope of workshop content ranges from new memory concepts in early research to the technology drivers currently in volume production as well as emerging technologies in development. The morning and afternoon technical sessions are organized in a manner that provides ample time for informal exchanges amongst presenters and attendees. The evening panel discussions will address hot topics in the memory and memory system field. Papers are solicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM, RRAM, MRAM, FRAM, embedded memories, system, and emerging memories), including but are not limited to:

 
Device Physics & Modeling
New Concepts & Disruptive Technologies
 
Cell Design & Novel Materials
Emerging Applications & Markets
 
Memory Process & Integration
SSD, Mobile & Automotive Applications
 
Circuit Design, Algorithms & Error Management
In-Memory & Neuromorphic Computing
 
Quality & Reliability
Memory-enabled Artificial Intelligence
 
System Architecture
No Tie
To promote informal discussions at the workshop, the organizing committee has decided on a “casual” dress code.
General Chair Technical Chair Finance Chair Publicity Chair
Haitao Liu Sangbum Kim Prashant Majhi Antonio Arreghini
Micron Seoul Nat'l Univ. Intel imec
In case of questions, please email at: imw.sangbum.kim@gmail.com